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/Linux-v5.10/drivers/hid/
Dhid-saitek.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Fixes the HID report descriptor by removing a non-existent axis and
7 * clearing the constant bit on the input reports for buttons and d-pad.
8 * (This module is based on "hid-ortek".)
12 * Fixes the mode button which cycles through three constantly pressed
25 #include "hid-ids.h"
33 int mode; member
39 unsigned long quirks = id->driver_data; in saitek_probe()
40 struct saitek_sc *ssc; in saitek_probe() local
43 ssc = devm_kzalloc(&hdev->dev, sizeof(*ssc), GFP_KERNEL); in saitek_probe()
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/Linux-v5.10/include/linux/
Datmel-ssc.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 void ssc_free(struct ssc_device *ssc);
30 /* SSC register offsets */
32 /* SSC Control Register */
45 /* SSC Clock Mode Register */
50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
92 /* SSC Transmit Clock Mode Register */
109 /* SSC Transmit Frame Mode Register */
134 /* SSC Receive Hold Register */
[all …]
/Linux-v5.10/sound/soc/atmel/
Datmel_ssc_dai.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
11 * Based on at91-ssc.c by
25 #include <linux/atmel-ssc.h>
32 #include "atmel-pcm.h"
39 * SSC PDC registers required by the PCM DMA engine.
56 * SSC & PDC status bits for transmit and receive.
136 * SSC interrupt handler. Passes PDC interrupts to the DMA
147 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) in atmel_ssc_interrupt()
148 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); in atmel_ssc_interrupt()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Atmel System-on-Chip"
7 the ATMEL SSC interface. You will also need
26 tristate "SoC PCM DAI support for AT91 SSC controller using PDC"
31 Say Y or M if you want to add support for Atmel SSC interface
32 in PDC mode configured using audio-graph-card in device-tree.
35 tristate "SoC PCM DAI support for AT91 SSC controller using DMA"
40 Say Y or M if you want to add support for Atmel SSC interface
41 in DMA mode configured using audio-graph-card in device-tree.
44 tristate "SoC Audio support for WM8731-based At91sam9g20 evaluation board"
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/Linux-v5.10/Documentation/devicetree/bindings/misc/
Datmel-ssc.txt1 * Atmel SSC driver.
4 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
5 - atmel,at91rm9200-ssc: support pdc transfer
6 - atmel,at91sam9g45-ssc: support dma transfer
7 - reg: Should contain SSC registers location and length
8 - interrupts: Should contain SSC interrupt
9 - clock-names: tuple listing input clock names.
11 - clocks: phandles to input clocks.
14 Required properties for devices compatible with "atmel,at91sam9g45-ssc":
15 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
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/Linux-v5.10/drivers/scsi/isci/
Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
197 /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
200 * MPC Manual PORT configuration mode is defined by the OEM configuration
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
229 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
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/Linux-v5.10/Documentation/devicetree/bindings/i2c/
Di2c-st.txt1 ST SSC binding, for I2C mode operation
4 - compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c"
5 - reg : Offset and length of the register set for the device
6 - interrupts : the interrupt specifier
7 - clock-names: Must contain "ssc".
8 - clocks: Must contain an entry for each name in clock-names. See the common
10 - A pinctrl state named "default" must be defined to set pins in mode of
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
17 - st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is
19 - st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is
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/Linux-v5.10/drivers/spi/
Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
9 * SPI master mode controller driver, used in STMicroelectronics devices.
26 /* SSC registers */
34 /* SSC Control */
49 /* SSC Interrupt Enable */
55 /* SSC SPI Controller */
60 /* SSC SPI current transaction */
75 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
78 count = spi_st->words_remaining; in ssc_write_tx_fifo()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
109 This enables support for the Quad SPI controller in master mode.
111 supports spi-mem interface.
138 is for the regular SPI controller. Slave mode operation is not also
181 this code to manage the per-word or per-transfer accesses to the
211 Flash over 1/2/4-bit wide bus. Enable this option if you have a
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/Linux-v5.10/drivers/i2c/busses/
Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C master mode controller driver, used in STMicroelectronics devices.
23 /* SSC registers */
47 /* SSC Control */
62 /* SSC Interrupt Enable */
76 /* SSC Status */
93 /* SSC I2C Control */
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
109 /* SSC Clear bit operation */
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/Linux-v5.10/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
57 /* PLL Test Mode register parameters */
61 /* PLL SSC step size offsets */
70 /* SSC step size parameters */
125 /* Test Mode common reset control parameters */
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
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/Linux-v5.10/drivers/scsi/mvsas/
Dmv_94xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
84 /* ports 1-3 follow after this */
87 /* ports 5-7 follow after this */
91 /* phys 1-3 follow after this */
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/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dbrcm-sata-phy.txt4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
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Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dti,cdce925.txt6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
21 - clocks: Points to a fixed parent clock that provides the input frequency.
22 - #clock-cells: From common clock bindings: Shall be 1.
25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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/Linux-v5.10/arch/arm/boot/dts/
Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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Dmpa1600.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * mpa1600.dts - Device Tree file for Phontech MPA 1600
7 /dts-v1/;
20 clock-frequency = <32768>;
24 clock-frequency = <18432000>;
36 compatible = "atmel,tcb-timer";
41 compatible = "atmel,tcb-timer";
47 phy-mode = "rmii";
51 ssc0: ssc@fffd0000 {
55 ssc1: ssc@fffd4000 {
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Dat91sam9g20ek_common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
13 stdout-path = "serial0:115200n8";
22 clock-frequency = <32768>;
26 clock-frequency = <18432000>;
42 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
55 compatible = "atmel,tcb-timer";
60 compatible = "atmel,tcb-timer";
66 pinctrl-0 =
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Dat91rm9200.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
22 interrupt-parent = <&aic>;
42 #address-cells = <1>;
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Dat91-sama5d4ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
8 /dts-v1/;
12 model = "Atmel SAMA5D4-EK";
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
36 pinctrl-names = "default";
37 pinctrl-0 = <
45 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
[all …]
Dsama5d3xmb_cmp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
10 compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
20 bus-width = <4>;
21 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
30 spi-max-frequency = <50000000>;
35 ssc0: ssc@f0008000 {
36 atmel,clk-from-rk-pin;
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/Linux-v5.10/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
303 u32 rate, bool ssc);
308 u32 rate, bool ssc);
365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
367 writew(val, ctx->base + offset); in cdns_regmap_write()
375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
377 *val = readw(ctx->base + offset); in cdns_regmap_read()
387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()
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/Linux-v5.10/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
278 bool ssc; member
294 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
302 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
305 return log2_in - 15; in brcm_pcie_encode_ibar_size()
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/Linux-v5.10/drivers/staging/mt7621-pci-phy/
Dpci-mt7621-phy.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
84 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
106 regmap_read(phy->regmap, reg, &val); in phy_read()
113 regmap_write(phy->regmap, reg, val); in phy_write()
131 if (phy->has_dual_port) { in mt7621_bypass_pipe_rst()
141 struct device *dev = phy->dev; in mt7621_set_phy_for_ssc()
147 /* Set PCIe Port PHY to disable SSC */ in mt7621_set_phy_for_ssc()
157 if (phy->has_dual_port) { in mt7621_set_phy_for_ssc()
163 /* Set Pre-divider ratio (for host mode) */ in mt7621_set_phy_for_ssc()
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/Linux-v5.10/drivers/phy/st/
Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <dt-bindings/phy/phy.h>
170 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
172 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
210 bool ssc; member
237 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
366 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
377 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
378 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
390 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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