Lines Matching +full:ssc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
9 * SPI master mode controller driver, used in STMicroelectronics devices.
26 /* SSC registers */
34 /* SSC Control */
49 /* SSC Interrupt Enable */
55 /* SSC SPI Controller */
60 /* SSC SPI current transaction */
75 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
78 count = spi_st->words_remaining; in ssc_write_tx_fifo()
81 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
82 if (spi_st->bytes_per_word == 1) { in ssc_write_tx_fifo()
83 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
85 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
86 word = *spi_st->tx_ptr++ | (word << 8); in ssc_write_tx_fifo()
89 writel_relaxed(word, spi_st->base + SSC_TBUF); in ssc_write_tx_fifo()
99 if (spi_st->words_remaining > FIFO_SIZE) in ssc_read_rx_fifo()
102 count = spi_st->words_remaining; in ssc_read_rx_fifo()
105 word = readl_relaxed(spi_st->base + SSC_RBUF); in ssc_read_rx_fifo()
107 if (spi_st->rx_ptr) { in ssc_read_rx_fifo()
108 if (spi_st->bytes_per_word == 1) { in ssc_read_rx_fifo()
109 *spi_st->rx_ptr++ = (uint8_t)word; in ssc_read_rx_fifo()
111 *spi_st->rx_ptr++ = (word >> 8); in ssc_read_rx_fifo()
112 *spi_st->rx_ptr++ = word & 0xff; in ssc_read_rx_fifo()
116 spi_st->words_remaining -= count; in ssc_read_rx_fifo()
126 spi_st->tx_ptr = t->tx_buf; in spi_st_transfer_one()
127 spi_st->rx_ptr = t->rx_buf; in spi_st_transfer_one()
129 if (spi->bits_per_word > 8) { in spi_st_transfer_one()
131 * Anything greater than 8 bits-per-word requires 2 in spi_st_transfer_one()
132 * bytes-per-word in the RX/TX buffers in spi_st_transfer_one()
134 spi_st->bytes_per_word = 2; in spi_st_transfer_one()
135 spi_st->words_remaining = t->len / 2; in spi_st_transfer_one()
137 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) { in spi_st_transfer_one()
139 * If transfer is even-length, and 8 bits-per-word, then in spi_st_transfer_one()
140 * implement as half-length 16 bits-per-word transfer in spi_st_transfer_one()
142 spi_st->bytes_per_word = 2; in spi_st_transfer_one()
143 spi_st->words_remaining = t->len / 2; in spi_st_transfer_one()
145 /* Set SSC_CTL to 16 bits-per-word */ in spi_st_transfer_one()
146 ctl = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_transfer_one()
147 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL); in spi_st_transfer_one()
149 readl_relaxed(spi_st->base + SSC_RBUF); in spi_st_transfer_one()
152 spi_st->bytes_per_word = 1; in spi_st_transfer_one()
153 spi_st->words_remaining = t->len; in spi_st_transfer_one()
156 reinit_completion(&spi_st->done); in spi_st_transfer_one()
160 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN); in spi_st_transfer_one()
163 wait_for_completion(&spi_st->done); in spi_st_transfer_one()
167 writel_relaxed(ctl, spi_st->base + SSC_CTL); in spi_st_transfer_one()
169 spi_finalize_current_transfer(spi->master); in spi_st_transfer_one()
171 return t->len; in spi_st_transfer_one()
176 gpio_free(spi->cs_gpio); in spi_st_cleanup()
179 /* the spi->mode bits understood by this driver: */
183 struct spi_st *spi_st = spi_master_get_devdata(spi->master); in spi_st_setup()
185 u32 hz = spi->max_speed_hz; in spi_st_setup()
186 int cs = spi->cs_gpio; in spi_st_setup()
190 dev_err(&spi->dev, "max_speed_hz unspecified\n"); in spi_st_setup()
191 return -EINVAL; in spi_st_setup()
195 dev_err(&spi->dev, "%d is not a valid gpio\n", cs); in spi_st_setup()
196 return -EINVAL; in spi_st_setup()
199 ret = gpio_request(cs, dev_name(&spi->dev)); in spi_st_setup()
201 dev_err(&spi->dev, "could not request gpio:%d\n", cs); in spi_st_setup()
205 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); in spi_st_setup()
209 spi_st_clk = clk_get_rate(spi_st->clk); in spi_st_setup()
214 dev_err(&spi->dev, in spi_st_setup()
216 ret = -EINVAL; in spi_st_setup()
220 spi_st->baud = spi_st_clk / (2 * sscbrg); in spi_st_setup()
221 if (sscbrg == BIT(16)) /* 16-bit counter wraps */ in spi_st_setup()
224 writel_relaxed(sscbrg, spi_st->base + SSC_BRG); in spi_st_setup()
226 dev_dbg(&spi->dev, in spi_st_setup()
228 hz, spi_st->baud, sscbrg); in spi_st_setup()
230 /* Set SSC_CTL and enable SSC */ in spi_st_setup()
231 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_setup()
234 if (spi->mode & SPI_CPOL) in spi_st_setup()
239 if (spi->mode & SPI_CPHA) in spi_st_setup()
244 if ((spi->mode & SPI_LSB_FIRST) == 0) in spi_st_setup()
249 if (spi->mode & SPI_LOOP) in spi_st_setup()
255 var |= (spi->bits_per_word - 1); in spi_st_setup()
260 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_setup()
263 readl_relaxed(spi_st->base + SSC_RBUF); in spi_st_setup()
281 if (spi_st->words_remaining) { in spi_st_irq()
285 writel_relaxed(0x0, spi_st->base + SSC_IEN); in spi_st_irq()
288 * before re-enabling interrupt in spi_st_irq()
290 readl(spi_st->base + SSC_IEN); in spi_st_irq()
291 complete(&spi_st->done); in spi_st_irq()
299 struct device_node *np = pdev->dev.of_node; in spi_st_probe()
305 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st)); in spi_st_probe()
307 return -ENOMEM; in spi_st_probe()
309 master->dev.of_node = np; in spi_st_probe()
310 master->mode_bits = MODEBITS; in spi_st_probe()
311 master->setup = spi_st_setup; in spi_st_probe()
312 master->cleanup = spi_st_cleanup; in spi_st_probe()
313 master->transfer_one = spi_st_transfer_one; in spi_st_probe()
314 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); in spi_st_probe()
315 master->auto_runtime_pm = true; in spi_st_probe()
316 master->bus_num = pdev->id; in spi_st_probe()
319 spi_st->clk = devm_clk_get(&pdev->dev, "ssc"); in spi_st_probe()
320 if (IS_ERR(spi_st->clk)) { in spi_st_probe()
321 dev_err(&pdev->dev, "Unable to request clock\n"); in spi_st_probe()
322 ret = PTR_ERR(spi_st->clk); in spi_st_probe()
326 ret = clk_prepare_enable(spi_st->clk); in spi_st_probe()
330 init_completion(&spi_st->done); in spi_st_probe()
333 spi_st->base = devm_platform_ioremap_resource(pdev, 0); in spi_st_probe()
334 if (IS_ERR(spi_st->base)) { in spi_st_probe()
335 ret = PTR_ERR(spi_st->base); in spi_st_probe()
339 /* Disable I2C and Reset SSC */ in spi_st_probe()
340 writel_relaxed(0x0, spi_st->base + SSC_I2C); in spi_st_probe()
341 var = readw_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
343 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
346 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
348 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
350 /* Set SSC into slave mode before reconfiguring PIO pins */ in spi_st_probe()
351 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
353 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
357 dev_err(&pdev->dev, "IRQ missing or invalid\n"); in spi_st_probe()
358 ret = -EINVAL; in spi_st_probe()
362 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0, in spi_st_probe()
363 pdev->name, spi_st); in spi_st_probe()
365 dev_err(&pdev->dev, "Failed to request irq %d\n", irq); in spi_st_probe()
370 pm_runtime_set_active(&pdev->dev); in spi_st_probe()
371 pm_runtime_enable(&pdev->dev); in spi_st_probe()
375 ret = devm_spi_register_master(&pdev->dev, master); in spi_st_probe()
377 dev_err(&pdev->dev, "Failed to register master\n"); in spi_st_probe()
384 pm_runtime_disable(&pdev->dev); in spi_st_probe()
385 clk_disable_unprepare(spi_st->clk); in spi_st_probe()
396 pm_runtime_disable(&pdev->dev); in spi_st_remove()
398 clk_disable_unprepare(spi_st->clk); in spi_st_remove()
400 pinctrl_pm_select_sleep_state(&pdev->dev); in spi_st_remove()
411 writel_relaxed(0, spi_st->base + SSC_IEN); in spi_st_runtime_suspend()
414 clk_disable_unprepare(spi_st->clk); in spi_st_runtime_suspend()
425 ret = clk_prepare_enable(spi_st->clk); in spi_st_runtime_resume()
464 { .compatible = "st,comms-ssc4-spi", },
471 .name = "spi-st",
481 MODULE_DESCRIPTION("STM SSC SPI driver");