Searched +full:sparx5 +full:- +full:sgpio +full:- +full:bank (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Lars Povlsen <lars.povlsen@microchip.com>21 pattern: "^gpio@[0-9a-f]+$"25 - microchip,sparx5-sgpio26 - mscc,ocelot-sgpio27 - mscc,luton-sgpio29 "#address-cells":[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/gpio/gpio.h>7 #include <dt-bindings/interrupt-controller/arm-gic.h>8 #include <dt-bindings/clock/microchip,sparx5.h>11 compatible = "microchip,sparx5";12 interrupt-parent = <&gic>;13 #address-cells = <2>;14 #size-cells = <1>;23 stdout-path = "serial0:115200n8";27 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later127 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()128 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()133 return bit + port * priv->bitcount; in sgpio_addr_to_pin()138 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; in sgpio_readl()146 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; in sgpio_writel()154 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; in sgpio_clrsetbits()165 int width = priv->bitcount - 1; in sgpio_configure_bitstream()168 switch (priv->properties->arch) { in sgpio_configure_bitstream()194 switch (priv->properties->arch) { in sgpio_configure_clock()[all …]
