Lines Matching +full:sparx5 +full:- +full:sgpio +full:- +full:bank
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
32 "#size-cells":
41 microchip,sgpio-port-ranges:
49 $ref: /schemas/types.yaml#/definitions/uint32-matrix
52 - description: |
56 - description: |
63 bus-frequency:
64 description: The sgpio controller frequency (Hz). This dictates
72 "^gpio@[0-1]$":
76 const: microchip,sparx5-sgpio-bank
80 The GPIO bank number. "0" is designates the input pin bank,
81 "1" the output bank.
84 gpio-controller: true
86 '#gpio-cells':
95 description: Specifies the sgpio IRQ (in parent controller)
98 interrupt-controller: true
100 '#interrupt-cells':
103 defined in include/dt-bindings/interrupt-controller/irq.h
113 - compatible
114 - reg
115 - gpio-controller
116 - '#gpio-cells'
117 - ngpios
124 - compatible
125 - reg
126 - clocks
127 - microchip,sgpio-port-ranges
128 - "#address-cells"
129 - "#size-cells"
132 - |
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "microchip,sparx5-sgpio";
139 pinctrl-0 = <&sgpio2_pins>;
140 pinctrl-names = "default";
142 microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
143 bus-frequency = <25000000>;
146 compatible = "microchip,sparx5-sgpio-bank";
147 gpio-controller;
148 #gpio-cells = <3>;
151 interrupt-controller;
152 #interrupt-cells = <3>;
155 compatible = "microchip,sparx5-sgpio-bank";
157 gpio-controller;
158 #gpio-cells = <3>;