Home
last modified time | relevance | path

Searched +full:smi +full:- +full:mdio (Results 1 – 25 of 30) sorted by relevance

12

/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/
Drealtek.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#
13 - Linus Walleij <linus.walleij@linaro.org>
17 switches. They can be controlled using different interfaces, like SMI,
18 MDIO or SPI.
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
22 not use the MDIO protocol. This binding defines how to specify the
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/
Dmvmdio.c2 * Driver for the MDIO interface of Marvell network interfaces.
4 * Since the MDIO interface of Marvell network interfaces is shared
7 * ports, but they in fact share the same SMI interface to access
8 * the MDIO bus). This driver is currently used by the mvneta and
13 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
56 * SMI Timeout measurements:
57 * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
58 * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
73 * but also reflects SMI completion), use that to wait for
74 * SMI access completion instead of polling the SMI busy bit.
[all …]
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
[all …]
/Linux-v6.1/drivers/net/dsa/realtek/
Drealtek-smi.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek Simple Management Interface (SMI) driver
5 * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels
6 * but the protocol is not MDIO at all. Instead it is a Realtek
7 * pecularity that need to bit-bang the lines in a special way to
12 * RTL8366 - The original version, apparently
13 * RTL8369 - Similar enough to have the same datsheet as RTL8366
14 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
16 * RTL8366S - Is this "RTL8366 super"?
17 * RTL8367 - Has an OpenWRT driver as well
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 tristate "Realtek MDIO interface driver"
26 through MDIO.
29 tristate "Realtek SMI interface driver"
36 through SMI.
44 Select to enable support for Realtek RTL8365MB-VC and RTL8367S.
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_NET_DSA_REALTEK_MDIO) += realtek-mdio.o
3 obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o
4 obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o
5 rtl8366-objs := rtl8366-core.o rtl8366rb.o
6 obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o
Drealtek.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Realtek SMI interface driver defines
5 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
32 * struct rtl8366_vlan_mc - Virtual LAN member configuration
53 struct gpio_desc *mdio; member
83 void *chip_data; /* Per-chip extra variant data */
87 * struct realtek_ops - vtable for the per-SMI-chiptype operations
Drealtek-mdio.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek MDIO interface driver
6 * RTL8366 - The original version, apparently
7 * RTL8369 - Similar enough to have the same datsheet as RTL8366
8 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
10 * RTL8366S - Is this "RTL8366 super"?
11 * RTL8367 - Has an OpenWRT driver as well
12 * RTL8368S - Seems to be an alternative name for RTL8366RB
13 * RTL8370 - Also uses SMI
19 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
[all …]
Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
11 * (SMI), which uses the MDIO/MDC lines.
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dcavium-mdio.txt1 * System Management Interface (SMI) / MDIO
4 - compatible: One of:
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
13 - #address-cells: Must be <1>.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
20 mdio@1180000001800 {
21 compatible = "cavium,octeon-3860-mdio";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dmarvell,armada-98dx3236-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
45 mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
24 mpp6 6 gpio, dev(cs3), xsmi(mdio)
35 mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
/Linux-v6.1/arch/arm/boot/dts/
Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
[all …]
Dbcm47094-asus-rt-ac88u.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (C) 2021-2022 Arınç ÜNAL <arinc.unal@arinc9.com>
6 /dts-v1/;
9 #include "bcm5301x-nand-cs0-bch8.dtsi"
12 compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
13 model = "Asus RT-AC88U";
34 compatible = "gpio-leds";
39 linux,default-trigger = "default-on";
42 wan-red {
55 trigger-sources = <&ehci_port2>;
[all …]
Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/Linux-v6.1/drivers/pinctrl/mvebu/
Dpinctrl-armada-39x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include "pinctrl-mvebu.h"
45 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
50 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
54 MPP_VAR_FUNCTION(7, "xsmi", "mdio", V_88F6920_PLUS)),
107 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
124 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
363 .compatible = "marvell,mv88f6920-pinctrl",
367 .compatible = "marvell,mv88f6925-pinctrl",
[all …]
Dpinctrl-armada-xp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
26 #include "pinctrl-mvebu.h"
189 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
235 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
243 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
371 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
467 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
471 MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS),
472 MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS),
[all …]
/Linux-v6.1/arch/arm64/boot/dts/marvell/
Darmada-37xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
34 psci-area@4000000 {
[all …]
Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dcharon.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&mpc5200_pic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
28 d-cache-line-size = <32>;
29 i-cache-line-size = <32>;
30 d-cache-size = <0x4000>; // L1, 16K
[all …]
/Linux-v6.1/drivers/net/dsa/mv88e6xxx/
Dchip.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
28 /* PVT limits for 4-bit port and 5-bit switch */
107 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
146 * ports 2-4 are not routet to pins.
149 /* Multi-chip Addressing Mode.
150 * Some chips respond to only 2 registers of its own SMI device address
151 * when it is non-zero, and use indirect access to internal registers.
154 /* Dual-chip Addressing Mode
155 * Some chips respond to only half of the 32 SMI addresses,
[all …]
Dchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88e6xxx Ethernet switch single-chip support
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
24 #include <linux/mdio.h>
44 #include "smi.h"
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { in assert_reg_lock()
49 dev_err(chip->dev, "Switch registers lock not held!\n"); in assert_reg_lock()
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", in mv88e6xxx_read()
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", in mv88e6xxx_write()
112 dev_err(chip->dev, "Timeout while waiting for switch\n"); in mv88e6xxx_wait_mask()
[all …]
/Linux-v6.1/arch/mips/cavium-octeon/
Docteon-platform.c6 * Copyright (C) 2004-2017 Cavium, Inc.
16 #include <asm/octeon/cvmx-helper-board.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
76 if (dev->of_node) { in octeon2_usb_clocks_start()
80 uctl_node = of_get_parent(dev->of_node); in octeon2_usb_clocks_start()
86 "refclk-frequency", &clock_rate); in octeon2_usb_clocks_start()
88 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); in octeon2_usb_clocks_start()
93 "refclk-type", &clock_type); in octeon2_usb_clocks_start()
201 * Step 4: Program the power-on reset field in the UCTL in octeon2_usb_clocks_start()
202 * clock-reset-control register. in octeon2_usb_clocks_start()
[all …]
/Linux-v6.1/drivers/net/ethernet/chelsio/cxgb3/
Dvsc8211.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
53 VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
134 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status()
144 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status()
210 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status_fiber()
220 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status_fiber()
276 * Enable/disable auto MDI/MDI-X in forced link speed mode.
376 SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T"); in t3_vsc8211_phy_prep()
[all …]
/Linux-v6.1/drivers/net/dsa/microchip/
Dksz_common.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
13 #include <linux/platform_data/microchip-ksz.h>
1089 * port map is NOT continuous. The per-port register
1456 if (chip->chip_id == prod_num) in ksz_lookup_info()
1467 dt_chip_data = of_device_get_match_data(dev->dev); in ksz_check_device_id()
1470 if (dt_chip_data->chip_id != dev->chip_id) { in ksz_check_device_id()
1471 dev_err(dev->dev, in ksz_check_device_id()
1473 dt_chip_data->dev_name, dev->info->dev_name); in ksz_check_device_id()
1474 return -ENODEV; in ksz_check_device_id()
[all …]

12