Lines Matching +full:smi +full:- +full:mdio

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Marvell 88E6xxx Ethernet switch single-chip definition
28 /* PVT limits for 4-bit port and 5-bit switch */
107  * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
146 	 * ports 2-4 are not routet to pins.
149 	/* Multi-chip Addressing Mode.
150 	 * Some chips respond to only 2 registers of its own SMI device address
151 	 * when it is non-zero, and use indirect access to internal registers.
154 	/* Dual-chip Addressing Mode
155 	 * Some chips respond to only half of the 32 SMI addresses,
156 	 * allowing two to coexist on the same SMI interface.
332 	/* Handles automatic disabling and re-enabling of the PHY
355 	/* List of mdio busses */
402 	/* Per-port timestamping resources. */
472 #define LINK_UNFORCED		-2
491 #define SPEED_UNFORCED		-2
492 #define DUPLEX_UNFORCED		-2
680 	/* Access port-scoped Precision Time Protocol registers */
732 	return chip->info->max_sid > 0 &&  in mv88e6xxx_has_stu()
733 		chip->info->ops->stu_loadpurge &&  in mv88e6xxx_has_stu()
734 		chip->info->ops->stu_getnext;  in mv88e6xxx_has_stu()
739 	return chip->info->pvt;  in mv88e6xxx_has_pvt()
744 	return !!chip->info->global2_addr;  in mv88e6xxx_has_lag()
749 	return chip->info->num_databases;  in mv88e6xxx_num_databases()
754 	return chip->info->num_macs;  in mv88e6xxx_num_macs()
759 	return chip->info->num_ports;  in mv88e6xxx_num_ports()
764 	return chip->info->max_vid;  in mv88e6xxx_max_vid()
769 	return chip->info->max_sid;  in mv88e6xxx_max_sid()
774 	return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);  in mv88e6xxx_port_mask()
779 	return chip->info->num_gpio;  in mv88e6xxx_num_gpio()
784 	return (chip->info->invalid_port_mask & BIT(port)) != 0;  in mv88e6xxx_is_invalid_port()
797 	mutex_lock(&chip->reg_lock);  in mv88e6xxx_reg_lock()
802 	mutex_unlock(&chip->reg_lock);  in mv88e6xxx_reg_unlock()