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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dti,phy-am654-serdes.yaml4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
7 title: TI AM654 SERDES binding
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
19 - ti,phy-am654-serdes
26 - const: serdes
46 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
48 ti,serdes-clk:
49 description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
57 description: Phandle to the SYSCON entry required for configuring SERDES lane function.
61 - description: Clock output names for SERDES 0
[all …]
Dphy-ocelot-serdes.txt1 Microsemi Ocelot SerDes muxing driver
5 space for setting up the SerDes to switch port muxing.
7 A SerDes X can be "muxed" to work with switch port Y or Z for example.
8 One specific SerDes can also be used as a PCIe interface.
10 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
12 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
24 - compatible: should be "mscc,vsc7514-serdes"
27 SerDes macro. The second defines the macro to use. They are
28 defined in dt-bindings/phy/phy-ocelot-serdes.h
32 serdes: serdes {
[all …]
Dmicrochip,sparx5-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
7 title: Microchip Sparx5 Serdes controller
13 The Sparx5 SERDES interfaces share the same basic functionality, but
16 The following list lists the SERDES features:
31 The SERDES6G is a high-speed SERDES interface, which can operate at
41 The SERDES10G is a high-speed SERDES interface, which can operate at
54 The SERDES25G is a high-speed SERDES interface, which can operate at
67 pattern: "^serdes@[0-9a-f]+$"
70 const: microchip,sparx5-serdes
78 - The main serdes input port
[all …]
Dti,phy-j721e-wiz.yaml8 title: TI J721E WIZ (SERDES Wrapper)
67 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
113 the SERDES.
138 provided by the SERDES.
152 "^serdes@[0-9a-f]+$":
155 WIZ node should have '1' subnode for the SERDES. It could be either
156 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
159 Torrent SERDES should follow the bindings specified in
224 serdes@5000000 {
226 reg-names = "serdes";
Dxlnx,zynqmp-psgtr.yaml61 - description: SERDES registers block
66 - const: serdes
99 reg-names = "serdes", "siou";
/Linux-v5.15/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi377 phys = <&serdes 13>;
384 phys = <&serdes 13>;
391 phys = <&serdes 13>;
398 phys = <&serdes 13>;
405 phys = <&serdes 14>;
412 phys = <&serdes 14>;
419 phys = <&serdes 14>;
426 phys = <&serdes 14>;
433 phys = <&serdes 15>;
440 phys = <&serdes 15>;
[all …]
Dsparx5_pcb134_board.dtsi719 phys = <&serdes 13>;
729 phys = <&serdes 14>;
738 phys = <&serdes 15>;
747 phys = <&serdes 16>;
756 phys = <&serdes 17>;
765 phys = <&serdes 18>;
774 phys = <&serdes 19>;
783 phys = <&serdes 20>;
792 phys = <&serdes 21>;
801 phys = <&serdes 22>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/net/
Damd-xgbe.txt8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
43 - amd,serdes-blwc: Baseline wandering correction enablement
46 - amd,serdes-cdr-rate: CDR rate speed selection
47 - amd,serdes-pq-skew: PQ (data sampling) skew
48 - amd,serdes-tx-amp: TX amplitude boost
49 - amd,serdes-dfe-tap-config: DFE taps available to run
50 - amd,serdes-dfe-tap-enable: DFE taps to enable
70 amd,serdes-blwc = <1>, <1>, <0>;
[all …]
Dmicrochip,sparx5-switch.yaml91 phandle of a Ethernet SerDes PHY. This defines which SerDes
96 This specifies the interface used by the Ethernet SerDes towards
107 points to the cuPHY used by the Ethernet SerDes.
113 the Ethernet SerDes.
171 phys = <&serdes 13>;
180 phys = <&serdes 29>;
189 phys = <&serdes 30>;
198 phys = <&serdes 31>;
207 phys = <&serdes 32>;
217 phys = <&serdes 0>;
Dhisilicon-hns-dsaf.txt17 The second region is SerDes base register and size(optional, only used when
18 serdes-syscon in port node does not exist). It is recommended using
19 serdes-syscon rather than this address.
40 - serdes-syscon: is syscon handle for SerDes register.
81 serdes-syscon = <&serdes>;
87 serdes-syscon = <&serdes>;
/Linux-v5.15/drivers/phy/mscc/
Dphy-ocelot-serdes.c3 * SerDes PHY driver for Microsemi Ocelot
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
60 static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode) in serdes_init_s6g() argument
89 ret = serdes_update_mcb_s6g(regmap, serdes); in serdes_init_s6g()
146 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
222 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
230 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
244 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
292 static int serdes_init_s1g(struct regmap *regmap, u8 serdes) in serdes_init_s1g() argument
296 ret = serdes_update_mcb_s1g(regmap, serdes); in serdes_init_s1g()
[all …]
/Linux-v5.15/drivers/net/ethernet/sfc/
Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/Linux-v5.15/drivers/net/ethernet/sfc/falcon/
Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/Linux-v5.15/drivers/phy/marvell/
DKconfig36 shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
55 shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be
66 shared serdes PHYs on Marvell Armada 7k/8k (in the CP110). Its serdes
/Linux-v5.15/drivers/phy/ti/
DKconfig25 tristate "TI AM654 SERDES support"
33 This option enables support for TI AM654 SerDes PHY used for
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
47 SoC. WIZ is a serdes wrapper used to configure some of the input
48 signals to the SERDES (Sierra/Torrent). This driver configures
/Linux-v5.15/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
99 phys = <&serdes 4 SERDES1G(2)>;
106 phys = <&serdes 5 SERDES1G(5)>;
113 phys = <&serdes 6 SERDES1G(3)>;
120 phys = <&serdes 9 SERDES1G(4)>;
/Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-intel.h11 /* SERDES Register */
16 /* SERDES defines */
19 #define SERDES_RST BIT(2) /* Serdes Reset */
20 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
/Linux-v5.15/drivers/net/dsa/mv88e6xxx/
Dserdes.c3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
18 #include "serdes.h"
176 dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err); in mv88e6352_serdes_pcs_get_state()
182 dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err); in mv88e6352_serdes_pcs_get_state()
349 dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err); in mv88e6352_serdes_irq_link()
436 /* The serdes power can't be controlled on this switch chip but we need in mv88e6185_serdes_power()
445 /* There are no configurable serdes lanes on this switch chip but we in mv88e6185_serdes_get_lane()
447 * mv88e6xxx_serdes_get_lane() know this is a serdes port. in mv88e6185_serdes_get_lane()
500 /* The serdes interrupts are enabled in the G2_INT_MASK register. We in mv88e6097_serdes_irq_enable()
640 /* Only Ports 0, 9 and 10 have SERDES lanes. Return the SERDES lane address
[all …]
/Linux-v5.15/include/linux/bcma/
Dbcma_driver_pci.h78 #define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
79 #define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
80 #define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
81 #define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
82 #define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
126 #define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
157 /* SERDES RX registers */
165 /* SERDES PLL registers */
187 /* MDIO devices (SERDES modules) */
/Linux-v5.15/arch/arm64/boot/dts/marvell/
Dcn9132-db.dtsi107 /* Generic PHY, providing serdes lanes */
157 /* Generic PHY, providing serdes lanes */
167 /* Generic PHY, providing serdes lanes */
176 /* Generic PHY, providing serdes lanes */
223 /* Generic PHY, providing serdes lanes */
/Linux-v5.15/drivers/infiniband/hw/hfi1/
Dfirmware.c165 /* the number of fabric SerDes on the SBus */
171 /* SBus fabric SerDes addresses, one set per HFI */
177 /* SBus PCIe SerDes addresses, one set per HFI */
193 /* SBus fabric SerDes broadcast addresses, one per HFI */
197 /* SBus PCIe SerDes broadcast addresses, one per HFI */
1084 * Turn off the SBus and fabric serdes spicos.
1087 * + Must be called after fabric serdes broadcast is set up.
1107 /* disable the fabric serdes spicos */ in turn_off_spicos()
1115 * Reset all of the fabric serdes for this HFI in preparation to take the
1118 * To do a reset, we need to write to to the serdes registers. Unfortunately,
[all …]
/Linux-v5.15/drivers/net/ethernet/amd/xgbe/
Dxgbe-phy-v1.c127 #define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
128 #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
129 #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
130 #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
131 #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
132 #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
134 /* Default SerDes settings */
208 /* SerDes UEFI configurable settings.
210 * SerDes settings. The values can be supplied as device
358 netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n", in xgbe_phy_complete_ratechange()
[all …]
/Linux-v5.15/drivers/infiniband/hw/qib/
Dqib_sd7220.c35 * This file contains all of the code that is specific to the SerDes
72 * various SerDes registers by IBC.
78 * used for PCIe, or the single SerDes used for IB.
390 * deals with registers and memory within the SerDes itself.
400 /* SERDES MPU reset recorded in D0 */ in qib_sd7220_init()
410 qib_dev_err(dd, "Failed to load IB SERDES image\n"); in qib_sd7220_init()
426 qib_dev_err(dd, "Failed to set IB SERDES early defaults\n"); in qib_sd7220_init()
437 qib_dev_err(dd, "Failed IB SERDES DAC trim\n"); in qib_sd7220_init()
449 qib_dev_err(dd, "Failed to set IB SERDES presets\n"); in qib_sd7220_init()
454 qib_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n"); in qib_sd7220_init()
[all …]
/Linux-v5.15/drivers/phy/samsung/
DKconfig93 tristate "Exynos5250 Sata SerDes/PHY driver"
102 Enable this to support SATA SerDes/Phy found on Samsung's
103 Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,

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