3  * Marvell 88E6xxx SERDES manipulation, via SMI bus
18 #include "serdes.h"
176 		dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err);  in mv88e6352_serdes_pcs_get_state()
182 		dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err);  in mv88e6352_serdes_pcs_get_state()
349 		dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err);  in mv88e6352_serdes_irq_link()
436 	/* The serdes power can't be controlled on this switch chip but we need  in mv88e6185_serdes_power()
445 	/* There are no configurable serdes lanes on this switch chip but we  in mv88e6185_serdes_get_lane()
447 	 * mv88e6xxx_serdes_get_lane() know this is a serdes port.  in mv88e6185_serdes_get_lane()
500 	/* The serdes interrupts are enabled in the G2_INT_MASK register. We  in mv88e6097_serdes_irq_enable()
640 /* Only Ports 0, 9 and 10 have SERDES lanes. Return the SERDES lane address
892 		dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err);  in mv88e6390_serdes_pcs_get_state_sgmii()
899 		dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err);  in mv88e6390_serdes_pcs_get_state_sgmii()
1048 		dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err);  in mv88e6390_serdes_irq_link_sgmii()
1065 		dev_err(chip->dev, "can't read Serdes STAT1: %d\n", err);  in mv88e6393x_serdes_irq_link_10g()
1219 	/* SERDES common registers */
1280 	 * Cannot clear PwrDn bit on SERDES if device is configured CPU_MGD  in mv88e6393x_serdes_port_errata()
1282 	 * Workaround: Set SERDES register 4.F002 bit 5=0 and bit 15=1.  in mv88e6393x_serdes_port_errata()
1284 	 * It seems that after this workaround the SERDES is automatically  in mv88e6393x_serdes_port_errata()
1309 	 * When a SERDES port is operating in 1000BASE-X or SGMII mode link may  in mv88e6393x_serdes_port_errata()
1310 	 * not come up after hardware reset or software reset of SERDES core.  in mv88e6393x_serdes_port_errata()
1311 	 * Workaround is to write SERDES register 4.F074.14=1 for only those  in mv88e6393x_serdes_port_errata()