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/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dralink,rt2880-pinmux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink rt2880 pinmux controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins
18 const: ralink,rt2880-pinmux
21 '-pins$':
24 '^(.*-)?pinmux$':
[all …]
Dbrcm,ns-pinmux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,bcm4708-pinmux
24 - brcm,bcm4709-pinmux
25 - brcm,bcm53012-pinmux
30 reg-names:
34 '-pins$':
[all …]
Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
[all …]
Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gareth Williams <gareth.williams.jx@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
[all …]
Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
[all …]
Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
[all …]
Drenesas,rza2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
23 const: "renesas,r7s9210-pinctrl" # RZ/A2M
28 gpio-controller: true
30 '#gpio-cells':
[all …]
Dpinctrl-mt8195.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
38 reg-names:
[all …]
Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
25 - const: renesas,r7s72100-ports # RZ/A1H
26 - items:
[all …]
Dpinctrl-mt8192.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
38 reg-names:
[all …]
Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <damien.lemoal@wdc.com>
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
30 - description: APB interface clock source
32 clock-names:
[all …]
Dapple,pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
20 - const: apple,t8103-pinctrl
21 - const: apple,pinctrl
29 gpio-controller: true
31 '#gpio-cells':
34 gpio-ranges:
[all …]
Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
[all …]
Dmt2712-evb.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
26 stdout-path = "serial0:921600n8";
30 compatible = "regulator-fixed";
31 regulator-name = "vproc_buck0";
32 regulator-min-microvolt = <1000000>;
33 regulator-max-microvolt = <1000000>;
37 compatible = "regulator-fixed";
[all …]
Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
21 stdout-path = "serial0:115200n8";
25 compatible = "pwm-backlight";
27 power-supply = <&bl_pp5000>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dat91-kizbox3-hs.dts1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
11 /dts-v1/;
12 #include "at91-kizbox3_common.dtsi"
15 model = "Overkiz KIZBOX3-HS";
16 compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
18 led-controller-1 {
21 led-1 {
25 led-2 {
29 led-3 {
[all …]
Dmt2701-evb.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
22 compatible = "mediatek,mt2701-cs42448-machine";
25 audio-routing =
42 mediatek,audio-codec = <&cs42448>;
43 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&aud_pins_default>;
[all …]
Dat91-sama7g5ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board
11 /dts-v1/;
12 #include "sama7g5-pinfunc.h"
14 #include <dt-bindings/mfd/atmel-flexcom.h>
15 #include <dt-bindings/input/input.h>
18 model = "Microchip SAMA7G5-EK";
23 stdout-path = "serial0:115200n8";
38 clock-frequency = <32768>;
42 clock-frequency = <24000000>;
[all …]
/Linux-v5.15/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinmux.h>
17 #include "pinmux.h"
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
[all …]
/Linux-v5.15/drivers/pinctrl/mediatek/
Dpinctrl-moore.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018 MediaTek Inc.
17 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf-generic.h>
23 #include "../pinmux.h"
24 #include "mtk-eint.h"
25 #include "pinctrl-mtk-common-v2.h"
40 #define PINCTRL_PIN_GROUP(name, id) \ argument
43 id##_pins, \
44 ARRAY_SIZE(id##_pins), \
[all …]
Dpinctrl-paris.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf-generic.h>
24 #include "../pinctrl-utils.h"
25 #include "../pinmux.h"
26 #include "mtk-eint.h"
27 #include "pinctrl-mtk-common-v2.h"
52 #define PINCTRL_PIN_GROUP(name, id) \ argument
55 id##_pins, \
56 ARRAY_SIZE(id##_pins), \
[all …]
/Linux-v5.15/drivers/pinctrl/renesas/
Dpinctrl-rza1.c1 // SPDX-License-Identifier: GPL-2.0
11 * This includes SoCs which are sub- or super- sets of this particular line,
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinmux.h>
32 #include "../pinmux.h"
34 #define DRIVER_NAME "pinctrl-rza1"
52 #define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT) argument
53 #define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT) argument
74 /* ----------------------------------------------------------------------------
75 * RZ/A1 pinmux flags
[all …]
/Linux-v5.15/drivers/mfd/
Dsi476x-i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mfd/si476x-i2c.c -- Core device driver for si476x MFD
21 #include <linux/mfd/si476x-core.h>
27 * si476x_core_config_pinmux() - pin function configuration function
39 dev_dbg(&core->client->dev, "Configuring pinmux\n"); in si476x_core_config_pinmux()
41 core->pinmux.dclk, in si476x_core_config_pinmux()
42 core->pinmux.dfs, in si476x_core_config_pinmux()
43 core->pinmux.dout, in si476x_core_config_pinmux()
44 core->pinmux.xout); in si476x_core_config_pinmux()
46 dev_err(&core->client->dev, in si476x_core_config_pinmux()
[all …]
/Linux-v5.15/drivers/pinctrl/freescale/
Dpinctrl-imx1.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * IMX pinmux core definitions
17 * struct imx1_pin - describes an IMX1/21/27 pin.
18 * @pin_id: ID of the described pin.
19 * @mux_id: ID of the mux setup.
20 * @config: Configuration of the pin (currently only pullup-enable).
29 * struct imx1_pin_group - describes an IMX pin group
43 * struct imx1_pmx_func - describes IMX pinmux functions

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