Lines Matching +full:pinmux +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0
11 * This includes SoCs which are sub- or super- sets of this particular line,
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinmux.h>
32 #include "../pinmux.h"
34 #define DRIVER_NAME "pinctrl-rza1"
52 #define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT) argument
53 #define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT) argument
74 /* ----------------------------------------------------------------------------
75 * RZ/A1 pinmux flags
79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
87 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
96 * rza1_swio_pin - describe a single pin that needs swio flag applied.
106 * rza1_swio_entry - describe a list of pins that needs swio flag applied
114 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
121 /* ----------------------------------------------------------------------------
122 * RZ/A1H (r7s72100) pinmux flags
296 /* RZ/A1H (r7s72100x) pinmux flags table */
302 /* ----------------------------------------------------------------------------
303 * RZ/A1L (r7s72102) pinmux flags
424 /* RZ/A1L (r7s72102x) pinmux flags table */
430 /* ----------------------------------------------------------------------------
434 * struct rza1_mux_conf - describes a pin multiplexing operation
436 * @id: the pin identifier from 0 to RZA1_NPINS
438 * @pin: pin id
439 * @mux_func: alternate function id number
444 u16 id; member
453 * struct rza1_port - describes a pin port
455 * This is mostly useful to lock register writes per-bank and not globally.
458 * @id: port number
464 unsigned int id; member
470 * struct rza1_pinctrl - RZ pincontroller device
473 * @mutex: protect [pinctrl|pinmux]_generic functions
499 /* ----------------------------------------------------------------------------
500 * RZ/A1 pinmux flags
511 for (i = 0; i < entry->npins; ++i) { in rza1_pinmux_get_bidir()
512 bidir_pin = &entry->pins[i]; in rza1_pinmux_get_bidir()
513 if (bidir_pin->pin == pin && bidir_pin->func == func) in rza1_pinmux_get_bidir()
529 for (i = 0; i < table->npins; ++i) { in rza1_pinmux_get_swio()
530 swio_pin = &table->pins[i]; in rza1_pinmux_get_swio()
531 if (swio_pin->port == port && swio_pin->pin == pin && in rza1_pinmux_get_swio()
532 swio_pin->func == func) in rza1_pinmux_get_swio()
533 return swio_pin->input; in rza1_pinmux_get_swio()
536 return -ENOENT; in rza1_pinmux_get_swio()
540 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
547 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data; in rza1_pinmux_get_flags()
548 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries; in rza1_pinmux_get_flags()
549 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries; in rza1_pinmux_get_flags()
565 /* ----------------------------------------------------------------------------
570 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
576 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); in rza1_set_bit()
590 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); in rza1_get_bit()
596 * rza1_pin_reset() - reset a pin to default initial state
598 * Reset pin state disabling input buffer and bi-directional control,
610 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_reset()
617 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_reset()
621 * rza1_pin_set_direction() - set I/O direction on a pin in port mode
635 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_set_direction()
646 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_set_direction()
654 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_set()
656 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_set()
665 * rza1_pin_mux_single() - configure pin multiplexing on a single pin
673 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port]; in rza1_pin_mux_single()
674 unsigned int pin = mux_conf->pin; in rza1_pin_mux_single()
675 u8 mux_func = mux_conf->mux_func; in rza1_pin_mux_single()
676 u8 mux_flags = mux_conf->mux_flags; in rza1_pin_mux_single()
681 /* SWIO pinmux flags coming from DT are high precedence */ in rza1_pin_mux_single()
682 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func, in rza1_pin_mux_single()
695 * Be careful here: the pin mux sub-nodes in device tree in rza1_pin_mux_single()
700 * ---------------------------------------------------- in rza1_pin_mux_single()
703 * PMC PFC PFCE PFCAE (mux_func - 1) in rza1_pin_mux_single()
712 * ---------------------------------------------------- in rza1_pin_mux_single()
714 mux_func -= 1; in rza1_pin_mux_single()
722 * to I/O direction specified by pin configuration -after- PMC has been in rza1_pin_mux_single()
736 /* ----------------------------------------------------------------------------
741 * rza1_gpio_request() - configure pin in port mode
760 * rza1_gpio_disable_free() - reset a pin
810 * rza1_gpio_get() - read a gpio pin value
813 * Requires bi-directional mode to work when reading the value of a pin
843 /* ----------------------------------------------------------------------------
848 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
849 * children sub-nodes
859 of_pins = of_find_property(np, "pinmux", NULL); in rza1_dt_node_pin_count()
861 return of_pins->length / sizeof(u32); in rza1_dt_node_pin_count()
865 of_pins = of_find_property(child, "pinmux", NULL); in rza1_dt_node_pin_count()
868 return -EINVAL; in rza1_dt_node_pin_count()
871 npins += of_pins->length / sizeof(u32); in rza1_dt_node_pin_count()
878 * rza1_parse_pmx_function() - parse a pin mux sub-node
881 * @np: of pmx sub-node
890 struct pinctrl_dev *pctldev = rza1_pctl->pctl; in rza1_parse_pinmux_node()
891 char const *prop_name = "pinmux"; in rza1_parse_pinmux_node()
902 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name); in rza1_parse_pinmux_node()
903 return -ENOENT; in rza1_parse_pinmux_node()
905 npins = of_pins->length / sizeof(u32); in rza1_parse_pinmux_node()
909 * this sub-node in rza1_parse_pinmux_node()
914 dev_err(rza1_pctl->dev, in rza1_parse_pinmux_node()
921 * Create a mask with pinmux flags from pin configuration; in rza1_parse_pinmux_node()
922 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction in rza1_parse_pinmux_node()
951 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK; in rza1_parse_pinmux_node()
952 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id); in rza1_parse_pinmux_node()
953 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id); in rza1_parse_pinmux_node()
954 mux_conf->mux_func = MUX_FUNC(of_pinconf); in rza1_parse_pinmux_node()
955 mux_conf->mux_flags = pinmux_flags; in rza1_parse_pinmux_node()
957 if (mux_conf->port >= RZA1_NPORTS || in rza1_parse_pinmux_node()
958 mux_conf->pin >= RZA1_PINS_PER_PORT) { in rza1_parse_pinmux_node()
959 dev_err(rza1_pctl->dev, in rza1_parse_pinmux_node()
961 mux_conf->port, mux_conf->pin, prop_name); in rza1_parse_pinmux_node()
962 return -EINVAL; in rza1_parse_pinmux_node()
965 grpins[i] = mux_conf->id; in rza1_parse_pinmux_node()
972 * rza1_dt_node_to_map() - map a pin mux node to a function/group
997 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n"); in rza1_dt_node_to_map()
998 return -EINVAL; in rza1_dt_node_to_map()
1004 * except that functions carry an array of per-pin mux configuration in rza1_dt_node_to_map()
1007 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs), in rza1_dt_node_to_map()
1009 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins), in rza1_dt_node_to_map()
1011 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL); in rza1_dt_node_to_map()
1014 return -ENOMEM; in rza1_dt_node_to_map()
1017 * Parse the pinmux node. in rza1_dt_node_to_map()
1018 * If the node does not contain "pinmux" property (-ENOENT) in rza1_dt_node_to_map()
1019 * that property shall be specified in all its children sub-nodes. in rza1_dt_node_to_map()
1025 if (ret == -ENOENT) in rza1_dt_node_to_map()
1041 grpname = np->name; in rza1_dt_node_to_map()
1044 mutex_lock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1048 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1059 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n", in rza1_dt_node_to_map()
1066 ret = -ENOMEM; in rza1_dt_node_to_map()
1070 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in rza1_dt_node_to_map()
1071 (*map)->data.mux.group = np->name; in rza1_dt_node_to_map()
1072 (*map)->data.mux.function = np->name; in rza1_dt_node_to_map()
1074 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1083 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1085 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n", in rza1_dt_node_to_map()
1105 /* ----------------------------------------------------------------------------
1106 * pinmux operations
1110 * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1127 return -EINVAL; in rza1_set_mux()
1131 return -EINVAL; in rza1_set_mux()
1133 mux_confs = (struct rza1_mux_conf *)func->data; in rza1_set_mux()
1134 for (i = 0; i < grp->num_pins; ++i) { in rza1_set_mux()
1153 /* ----------------------------------------------------------------------------
1163 if (!of_property_read_bool(child, "gpio-controller")) in rza1_count_gpio_chips()
1173 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1175 * The gpio controller subnode shall provide a "gpio-ranges" list property as
1179 * @np: of gpio-controller node
1188 const char *list_name = "gpio-ranges"; in rza1_parse_gpiochip()
1196 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n", in rza1_parse_gpiochip()
1202 * Find out on which port this gpio-chip maps to by inspecting the in rza1_parse_gpiochip()
1203 * second argument of the "gpio-ranges" property. in rza1_parse_gpiochip()
1208 dev_err(rza1_pctl->dev, in rza1_parse_gpiochip()
1210 return -EINVAL; in rza1_parse_gpiochip()
1214 chip->base = -1; in rza1_parse_gpiochip()
1215 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn", in rza1_parse_gpiochip()
1217 if (!chip->label) in rza1_parse_gpiochip()
1218 return -ENOMEM; in rza1_parse_gpiochip()
1220 chip->ngpio = of_args.args[2]; in rza1_parse_gpiochip()
1221 chip->of_node = np; in rza1_parse_gpiochip()
1222 chip->parent = rza1_pctl->dev; in rza1_parse_gpiochip()
1224 range->id = gpioport; in rza1_parse_gpiochip()
1225 range->name = chip->label; in rza1_parse_gpiochip()
1226 range->pin_base = range->base = pinctrl_base; in rza1_parse_gpiochip()
1227 range->npins = of_args.args[2]; in rza1_parse_gpiochip()
1228 range->gc = chip; in rza1_parse_gpiochip()
1230 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip, in rza1_parse_gpiochip()
1231 &rza1_pctl->ports[gpioport]); in rza1_parse_gpiochip()
1235 pinctrl_add_gpio_range(rza1_pctl->pctl, range); in rza1_parse_gpiochip()
1237 dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", in rza1_parse_gpiochip()
1238 chip->label, chip->ngpio); in rza1_parse_gpiochip()
1244 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1250 struct device_node *np = rza1_pctl->dev->of_node; in rza1_gpio_register()
1260 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n"); in rza1_gpio_register()
1264 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips, in rza1_gpio_register()
1266 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips, in rza1_gpio_register()
1269 return -ENOMEM; in rza1_gpio_register()
1273 if (!of_property_read_bool(child, "gpio-controller")) in rza1_gpio_register()
1286 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i); in rza1_gpio_register()
1292 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1304 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins), in rza1_pinctrl_register()
1306 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports), in rza1_pinctrl_register()
1309 return -ENOMEM; in rza1_pinctrl_register()
1311 rza1_pctl->pins = pins; in rza1_pinctrl_register()
1312 rza1_pctl->desc.pins = pins; in rza1_pinctrl_register()
1313 rza1_pctl->desc.npins = RZA1_NPINS; in rza1_pinctrl_register()
1314 rza1_pctl->ports = ports; in rza1_pinctrl_register()
1321 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, in rza1_pinctrl_register()
1322 "P%u-%u", port, pin); in rza1_pinctrl_register()
1324 return -ENOMEM; in rza1_pinctrl_register()
1329 * they provide per-port lock and logical base address. in rza1_pinctrl_register()
1333 ports[port_id].id = port_id; in rza1_pinctrl_register()
1334 ports[port_id].base = rza1_pctl->base; in rza1_pinctrl_register()
1340 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc, in rza1_pinctrl_register()
1341 rza1_pctl, &rza1_pctl->pctl); in rza1_pinctrl_register()
1343 dev_err(rza1_pctl->dev, in rza1_pinctrl_register()
1348 ret = pinctrl_enable(rza1_pctl->pctl); in rza1_pinctrl_register()
1350 dev_err(rza1_pctl->dev, in rza1_pinctrl_register()
1357 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n"); in rza1_pinctrl_register()
1369 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL); in rza1_pinctrl_probe()
1371 return -ENOMEM; in rza1_pinctrl_probe()
1373 rza1_pctl->dev = &pdev->dev; in rza1_pinctrl_probe()
1375 rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0); in rza1_pinctrl_probe()
1376 if (IS_ERR(rza1_pctl->base)) in rza1_pinctrl_probe()
1377 return PTR_ERR(rza1_pctl->base); in rza1_pinctrl_probe()
1379 mutex_init(&rza1_pctl->mutex); in rza1_pinctrl_probe()
1383 rza1_pctl->desc.name = DRIVER_NAME; in rza1_pinctrl_probe()
1384 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops; in rza1_pinctrl_probe()
1385 rza1_pctl->desc.pmxops = &rza1_pinmux_ops; in rza1_pinctrl_probe()
1386 rza1_pctl->desc.owner = THIS_MODULE; in rza1_pinctrl_probe()
1387 rza1_pctl->data = of_device_get_match_data(&pdev->dev); in rza1_pinctrl_probe()
1393 dev_info(&pdev->dev, in rza1_pinctrl_probe()
1402 .compatible = "renesas,r7s72100-ports",
1407 .compatible = "renesas,r7s72102-ports",