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/Linux-v5.10/arch/powerpc/platforms/8xx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
42 bool "Analogue & Micro Adder 875"
45 This enables support for the Analogue & Micro Adder 875
56 menu "Freescale Ethernet driver platform-specific options"
76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
77 (often 2-nd UART) will not work if this is enabled.
83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
84 (often 1-nd UART) will not work if this is enabled.
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
Dpipeline.json10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc…
40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/Linux-v5.10/arch/arm/kernel/
Dperf_event_v6.c1 // SPDX-License-Identifier: GPL-2.0
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
19 * - disable the counter's interrupt generation (each counter has it's
24 * - enable the counter's interrupt generation.
25 * - set the new event type.
30 * ignoring that counter. When re-enabling, we have to reset the value and
104 * The ARM performance counters can count micro DTLB misses, micro ITLB
105 * misses and main TLB misses. There isn't an event for TLB misses, so
106 * use the micro misses here and if users want the main TLB misses they
167 * The ARM performance counters can count micro DTLB misses, micro ITLB
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/iommu/
Drenesas,ipmmu-vmsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VMSA-Compatible IOMMU
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 connected to the IPMMU through a port called micro-TLB.
20 - items:
21 - enum:
22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6
[all …]
Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
21 here, there must be a corresponding entry in clock-names
[all …]
/Linux-v5.10/drivers/edac/
Dmce_amd.c1 // SPDX-License-Identifier: GPL-2.0-only
71 "PFB non-cacheable bit parity error",
101 "Link-defined sync error packets detected on HT link",
151 "Level 1 TLB parity error",
164 "Level 2 TLB parity error",
174 "An ECC error was detected on a data cache read-modify-write by a store",
179 "An ECC error was detected on an EMEM read-modify-write by a store",
180 "A parity error was detected in an L1 TLB entry by any access",
181 "A parity error was detected in an L2 TLB entry by any access",
200 "IC Microtag or Full Tag Multi-hit Error",
[all …]
/Linux-v5.10/arch/mips/mm/
Dtlb-funcs.S6 * Micro-assembler generated tlb handler functions.
10 * Based on mm/page-funcs.c
12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
/Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen1/
Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
176 "ScaleUnit": "6.1e-5MiB"
/Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen2/
Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
176 "ScaleUnit": "6.1e-5MiB"
/Linux-v5.10/arch/arc/mm/
Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14 * entry, so that it doesn't knock out it's I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
[all …]
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for ARC700
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gmc.h2 * Copyright 2018 Advanced Micro Devices, Inc.
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
111 /* flush the vm tlb via mmio */
114 /* flush the vm tlb via pasid */
117 /* flush the vm tlb via ring */
120 /* Change the VMID -> PASID mapping */
134 /* get the amount of memory used by the vbios for pre-OS console */
144 /* physical node (0-3) */
146 /* number of nodes (0-4) */
245 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((ad…
[all …]
Dgfxhub_v1_0.c2 * Copyright 2016 Advanced Micro Devices, Inc.
41 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; in gfxhub_v1_0_setup_vm_pt_regs()
44 hub->ctx_addr_distance * vmid, in gfxhub_v1_0_setup_vm_pt_regs()
48 hub->ctx_addr_distance * vmid, in gfxhub_v1_0_setup_vm_pt_regs()
54 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_0_init_gart_aperture_regs()
59 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
61 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
64 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
66 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
[all …]
Dgfxhub_v2_0.c2 * Copyright 2019 Advanced Micro Devices, Inc.
82 dev_err(adev->dev, in gfxhub_v2_0_print_l2_protection_fault_status()
85 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", in gfxhub_v2_0_print_l2_protection_fault_status()
88 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", in gfxhub_v2_0_print_l2_protection_fault_status()
91 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", in gfxhub_v2_0_print_l2_protection_fault_status()
94 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", in gfxhub_v2_0_print_l2_protection_fault_status()
97 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", in gfxhub_v2_0_print_l2_protection_fault_status()
100 dev_err(adev->dev, "\t RW: 0x%lx\n", in gfxhub_v2_0_print_l2_protection_fault_status()
123 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; in gfxhub_v2_0_setup_vm_pt_regs()
126 hub->ctx_addr_distance * vmid, in gfxhub_v2_0_setup_vm_pt_regs()
[all …]
Dgfxhub_v2_1.c2 * Copyright 2019 Advanced Micro Devices, Inc.
82 dev_err(adev->dev, in gfxhub_v2_1_print_l2_protection_fault_status()
85 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", in gfxhub_v2_1_print_l2_protection_fault_status()
88 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", in gfxhub_v2_1_print_l2_protection_fault_status()
91 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", in gfxhub_v2_1_print_l2_protection_fault_status()
94 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", in gfxhub_v2_1_print_l2_protection_fault_status()
97 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", in gfxhub_v2_1_print_l2_protection_fault_status()
100 dev_err(adev->dev, "\t RW: 0x%lx\n", in gfxhub_v2_1_print_l2_protection_fault_status()
123 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; in gfxhub_v2_1_setup_vm_pt_regs()
126 hub->ctx_addr_distance * vmid, in gfxhub_v2_1_setup_vm_pt_regs()
[all …]
Dgmc_v10_0.c2 * Copyright 2019 Advanced Micro Devices, Inc.
96 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
100 addr = (u64)entry->src_data[0] << 12; in gmc_v10_0_process_interrupt()
101 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v10_0_process_interrupt()
109 if (entry->vmid_src == AMDGPU_GFXHUB_0) in gmc_v10_0_process_interrupt()
110 RREG32(hub->vm_l2_pro_fault_status); in gmc_v10_0_process_interrupt()
112 status = RREG32(hub->vm_l2_pro_fault_status); in gmc_v10_0_process_interrupt()
113 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); in gmc_v10_0_process_interrupt()
120 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v10_0_process_interrupt()
122 dev_err(adev->dev, in gmc_v10_0_process_interrupt()
[all …]
Dgmc_v9_0.c2 * Copyright 2016 Advanced Micro Devices, Inc.
426 if (adev->asic_type >= CHIP_VEGA20) in gmc_v9_0_ecc_interrupt_state()
485 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
486 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
488 reg = hub->vm_context0_cntl + i; in gmc_v9_0_vm_fault_interrupt_state()
496 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
497 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
499 reg = hub->vm_context0_cntl + i; in gmc_v9_0_vm_fault_interrupt_state()
517 bool retry_fault = !!(entry->src_data[1] & 0x80); in gmc_v9_0_process_interrupt()
523 addr = (u64)entry->src_data[0] << 12; in gmc_v9_0_process_interrupt()
[all …]
/Linux-v5.10/Documentation/firmware-guide/acpi/apei/
Doutput_format.rst1 .. SPDX-License-Identifier: GPL-2.0
55 [cache error][, TLB error][, bus error][, micro-architectural error]
81 unknown | no error | single-bit ECC | multi-bit ECC | \
82 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
106 downstream switch port | PCIe to PCI/PCI-X bridge | \
107 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
121 Replay Timer Timeout | Advisory Non-Fatal
/Linux-v5.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_crat.h2 * Copyright 2014 Advanced Micro Devices, Inc.
45 #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
141 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
174 * HSA TLB Affinity structure and definitions
277 uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
282 * HSA generic sub-type header
/Linux-v5.10/drivers/iommu/
Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-iommu.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
30 #include <asm/dma-iommu.h>
33 #define arm_iommu_attach_device(...) -ENODEV
39 #define IPMMU_CTX_INVALID -1
96 /* -----------------------------------------------------------------------------
[all …]
/Linux-v5.10/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
129 The ARM series is a line of low-power-consumption RISC chip designs
131 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
132 manufactured, but legacy ARM-based PC hardware remains popular in
242 Patch phys-to-virt and virt-to-phys translation functions at
246 This can only be used with non-XIP MMU kernels where the base
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 bool "EBSA-110"
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmont/
Dpipeline.json62 …nts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
83 …ed includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, tho…
113 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
119 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
146 …ssued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the u…
188 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
194 "BriefDescription": "Self-Modifying Code detected"
/Linux-v5.10/arch/sh/kernel/
Dhead_32.S1 /* SPDX-License-Identifier: GPL-2.0
42 .skip PAGE_SIZE - empty_zero_page - 1b
54 * Hardware (including on-chip modules) may or may not be initialized.
74 * We do this early on for SH-4A as a micro-optimization,
93 * When we boot in 32-bit MMU mode there are 2 PMB entries already
97 * ---------------------------------------------------------------
117 * mapping are unsupported in 32-bit mode and must specify their caching
138 mov.l .LMMUCR, r1 /* Flush the TLB */
313 mov.l r0,@-r2
/Linux-v5.10/drivers/firmware/efi/
Dcper-x86.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018, Advanced Micro Devices, Inc.
144 "32-bit Mode Execution Context",
145 "64-bit Mode Execution Context",
147 "32-bit Mode Debug Registers (DR0-DR7)",
148 "64-bit Mode Debug Registers (DR0-DR7)",
206 * CACHE has more operation types than TLB or BUS, though the in print_err_info()
264 if (proc->validation_bits & VALID_LAPIC_ID) in cper_print_proc_ia()
265 printk("%sLocal APIC_ID: 0x%llx\n", pfx, proc->lapic_id); in cper_print_proc_ia()
267 if (proc->validation_bits & VALID_CPUID_INFO) { in cper_print_proc_ia()
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmontplus/
Dpipeline.json75 …nts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
98 …ed includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, tho…
134 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
142 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
165 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature"
183 …ssued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the u…
231 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
239 "BriefDescription": "Self-Modifying Code detected"
267 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store…

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