1 // SPDX-License-Identifier: GPL-2.0-only
71 	"PFB non-cacheable bit parity error",
101 	"Link-defined sync error packets detected on HT link",
151 	"Level 1 TLB parity error",
164 	"Level 2 TLB parity error",
174 	"An ECC error was detected on a data cache read-modify-write by a store",
179 	"An ECC error was detected on an EMEM read-modify-write by a store",
180 	"A parity error was detected in an L1 TLB entry by any access",
181 	"A parity error was detected in an L2 TLB entry by any access",
200 	"IC Microtag or Full Tag Multi-hit Error",
209 	"L1 BTB Multi-Match Error",
210 	"L2 BTB Multi-Match Error",
214 	"L1-TLB Multi-Hit",
215 	"L2-TLB Multi-Hit",
221 	"L2M Tag Multiple-Way-Hit error",
228 	"Micro-op cache tag parity error",
229 	"Micro-op cache data parity error",
231 	"Micro-op queue parity error",
236 	"Micro-op buffer parity error",
269 	"Shadow Tag Macro Multi-way-hit Error",
271 	"L3M Tag Multi-way-hit Error",
350 	"TLB Bank 0 parity error",
351 	"TLB Bank 1 parity error",
397 	"CCIX Read Response with Status: Non-Data Error",
398 	"CCIX Write Response with Status: Non-Data Error",
400 	"CCIX Non-okay write response with data error",
502 			pr_cont("TLB reload.\n");  in cat_mc0_mce()
575 	u16 ec = EC(m->status);  in decode_mc0_mce()
576 	u8 xec = XEC(m->status, xec_mask);  in decode_mc0_mce()
580 	/* TLB error signatures are the same across families */  in decode_mc0_mce()
583 			pr_cont("%s TLB %s.\n", LL_MSG(ec),  in decode_mc0_mce()
666 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);  in f15h_mc1_mce()
670 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);  in f15h_mc1_mce()
674 		pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);  in f15h_mc1_mce()
685 	u16 ec = EC(m->status);  in decode_mc1_mce()
686 	u8 xec = XEC(m->status, xec_mask);  in decode_mc1_mce()
691 		pr_cont("%s TLB %s.\n", LL_MSG(ec),  in decode_mc1_mce()
694 		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));  in decode_mc1_mce()
725 			pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",  in k8_mc2_mce()
755 			pr_cont("Data parity TLB read error.\n");  in f15h_mc2_mce()
757 			pr_cont("Poison data provided for TLB fill.\n");  in f15h_mc2_mce()
768 			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);  in f15h_mc2_mce()
772 			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);  in f15h_mc2_mce()
831 	u16 ec = EC(m->status);  in decode_mc2_mce()
832 	u8 xec = XEC(m->status, xec_mask);  in decode_mc2_mce()
842 	u16 ec = EC(m->status);  in decode_mc3_mce()
843 	u8 xec = XEC(m->status, xec_mask);  in decode_mc3_mce()
871 	unsigned int fam = x86_family(m->cpuid);  in decode_mc4_mce()
872 	int node_id = amd_get_nb_id(m->extcpu);  in decode_mc4_mce()
873 	u16 ec = EC(m->status);  in decode_mc4_mce()
874 	u8 xec = XEC(m->status, 0x1f);  in decode_mc4_mce()
920 	pr_cont("%s.\n", mc4_mce_desc[xec - offset]);  in decode_mc4_mce()
929 	unsigned int fam = x86_family(m->cpuid);  in decode_mc5_mce()
930 	u16 ec = EC(m->status);  in decode_mc5_mce()
931 	u8 xec = XEC(m->status, xec_mask);  in decode_mc5_mce()
961 	u8 xec = XEC(m->status, xec_mask);  in decode_mc6_mce()
981 	u8 xec = XEC(m->status, xec_mask);  in decode_smca_error()
983 	if (m->bank >= ARRAY_SIZE(smca_banks))  in decode_smca_error()
986 	hwid = smca_banks[m->bank].hwid;  in decode_smca_error()
990 	bank_type = hwid->bank_type;  in decode_smca_error()
993 		pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);  in decode_smca_error()
1006 		decode_dram_ecc(cpu_to_node(m->extcpu), m);  in decode_smca_error()
1024 		pr_cont(", mem-tx: %s", R4_MSG(ec));  in amd_decode_err_code()
1027 			pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));  in amd_decode_err_code()
1035 	if (m->status & MCI_STATUS_UC) {  in decode_error_status()
1036 		if (m->status & MCI_STATUS_PCC)  in decode_error_status()
1038 		if (m->mcgstatus & MCG_STATUS_RIPV)  in decode_error_status()
1043 	if (m->status & MCI_STATUS_DEFERRED)  in decode_error_status()
1053 	unsigned int fam = x86_family(m->cpuid);  in amd_decode_mce()
1056 	if (m->kflags & MCE_HANDLED_CEC)  in amd_decode_mce()
1062 		m->extcpu,  in amd_decode_mce()
1063 		fam, x86_model(m->cpuid), x86_stepping(m->cpuid),  in amd_decode_mce()
1064 		m->bank,  in amd_decode_mce()
1065 		((m->status & MCI_STATUS_OVER)	? "Over"  : "-"),  in amd_decode_mce()
1066 		((m->status & MCI_STATUS_UC)	? "UE"	  :  in amd_decode_mce()
1067 		 (m->status & MCI_STATUS_DEFERRED) ? "-"  : "CE"),  in amd_decode_mce()
1068 		((m->status & MCI_STATUS_MISCV)	? "MiscV" : "-"),  in amd_decode_mce()
1069 		((m->status & MCI_STATUS_ADDRV)	? "AddrV" : "-"),  in amd_decode_mce()
1070 		((m->status & MCI_STATUS_PCC)	? "PCC"	  : "-"));  in amd_decode_mce()
1074 		u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);  in amd_decode_mce()
1078 			pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));  in amd_decode_mce()
1080 		pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));  in amd_decode_mce()
1084 	ecc = (m->status >> 45) & 0x3;  in amd_decode_mce()
1089 		pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));  in amd_decode_mce()
1092 		if (fam != 0x15 || m->bank != 4)  in amd_decode_mce()
1093 			pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));  in amd_decode_mce()
1097 		pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));  in amd_decode_mce()
1099 	pr_cont("]: 0x%016llx\n", m->status);  in amd_decode_mce()
1101 	if (m->status & MCI_STATUS_ADDRV)  in amd_decode_mce()
1102 		pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);  in amd_decode_mce()
1104 	if (m->ppin)  in amd_decode_mce()
1105 		pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin);  in amd_decode_mce()
1108 		pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);  in amd_decode_mce()
1110 		if (m->status & MCI_STATUS_SYNDV)  in amd_decode_mce()
1111 			pr_cont(", Syndrome: 0x%016llx", m->synd);  in amd_decode_mce()
1119 	if (m->tsc)  in amd_decode_mce()
1120 		pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);  in amd_decode_mce()
1126 	switch (m->bank) {  in amd_decode_mce()
1160 	amd_decode_err_code(m->status & 0xffff);  in amd_decode_mce()
1162 	m->kflags |= MCE_HANDLED_EDAC;  in amd_decode_mce()
1175 	if (c->x86_vendor != X86_VENDOR_AMD &&  in mce_amd_init()
1176 	    c->x86_vendor != X86_VENDOR_HYGON)  in mce_amd_init()
1177 		return -ENODEV;  in mce_amd_init()
1184 	switch (c->x86) {  in mce_amd_init()
1216 		xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;  in mce_amd_init()
1233 		return -EINVAL;  in mce_amd_init()
1236 		printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);  in mce_amd_init()
1237 		return -EINVAL;  in mce_amd_init()
1241 	pr_info("MCE: In-kernel MCE decoding enabled.\n");  in mce_amd_init()
1256 MODULE_ALIAS("edac-mce-amd");