Searched +full:ipq806x +full:- +full:usb +full:- +full:phy +full:- +full:hs (Results 1 – 5 of 5) sorted by relevance
| /Linux-v5.15/Documentation/devicetree/bindings/phy/ |
| D | qcom,ipq806x-usb-phy-hs.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-hs
21 "#phy-cells":
[all …]
|
| /Linux-v5.15/drivers/phy/qualcomm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm IPQ4019 USB PHY driver"
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
29 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
36 tristate "Qualcomm PCIe Gen2 PHY Driver"
40 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
[all …]
|
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
5 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
6 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
7 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
8 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
9 obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
10 obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
[all …]
|
| D | phy-qcom-ipq806x-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
14 /* USB QSCRATCH Hardware registers */
35 /* USB QSCRATCH Hardware registers */
53 /* SSPHY control registers - Does this need 0x30? */
132 * @base - QCOM DWC3 PHY base virtual address.
133 * @offset - register offset.
134 * @mask - register bitmask specifying what should be updated
135 * @val - value to write.
141 u32 write_val, tmp = readl(phy_dwc3->base + offset); in usb_phy_write_readback()
[all …]
|
| /Linux-v5.15/arch/arm/boot/dts/ |
| D | qcom-ipq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
[all …]
|
