| /Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | fanpwm.c | 44 u32 divs, duty; in nvkm_fanpwm_get() local
47 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
74 duty = ((divs * percent) + 99) / 100; in nvkm_fanpwm_set()
76 duty = divs - duty; in nvkm_fanpwm_set()
78 ret = therm->func->pwm_set(therm, fan->func.line, divs, duty); in nvkm_fanpwm_set()
91 u32 divs, duty; in nvkm_fanpwm_create() local
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| D | fan.c | 39 int duty; in nvkm_fan_update() local
52 /* check that we're not already at the target duty cycle */ in nvkm_fan_update()
53 duty = fan->get(therm); in nvkm_fan_update()
54 if (duty == target) { in nvkm_fan_update()
60 if (!immediate && duty >= 0) { in nvkm_fan_update()
65 if (duty < target) in nvkm_fan_update()
66 duty = min(duty + 3, target); in nvkm_fan_update()
67 else if (duty > target) in nvkm_fan_update()
68 duty = max(duty - 3, target); in nvkm_fan_update()
70 duty = target; in nvkm_fan_update()
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| D | base.c | 44 u16 duty, i; in nvkm_therm_update_trip() local
59 duty = cur_trip->fan_duty; in nvkm_therm_update_trip()
62 duty = 0; in nvkm_therm_update_trip()
66 return duty; in nvkm_therm_update_trip()
74 u16 duty; in nvkm_therm_compute_linear_duty() local
83 duty = (temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
84 duty *= (therm->fan->bios.max_duty - therm->fan->bios.min_duty); in nvkm_therm_compute_linear_duty()
85 duty /= (linear_max_temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
86 duty += therm->fan->bios.min_duty; in nvkm_therm_compute_linear_duty()
87 return duty; in nvkm_therm_compute_linear_duty()
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| D | gf119.c | 67 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gf119_fan_pwm_get() argument
76 *duty = nvkm_rd32(device, 0x00e118 + (indx * 8)); in gf119_fan_pwm_get()
81 *duty = nvkm_rd32(device, 0x0200dc) & 0x1fff; in gf119_fan_pwm_get()
89 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gf119_fan_pwm_set() argument
97 nvkm_wr32(device, 0x00e118 + (indx * 8), duty | 0x80000000); in gf119_fan_pwm_set()
100 nvkm_wr32(device, 0x0200dc, duty | 0x40000000); in gf119_fan_pwm_set()
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| D | fantog.c | 46 int duty; in nvkm_fantog_update() local
53 duty = !nvkm_gpio_get(gpio, 0, DCB_GPIO_FAN, 0xff); in nvkm_fantog_update()
54 nvkm_gpio_set(gpio, 0, DCB_GPIO_FAN, 0xff, duty); in nvkm_fantog_update()
56 if (percent != (duty * 100)) { in nvkm_fantog_update()
58 if (!duty) in nvkm_fantog_update()
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| /Linux-v5.10/drivers/pwm/ |
| D | pwm-renesas-tpu.c | 78 u16 duty; member
179 tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); in tpu_pwm_timer_start()
183 pwm->channel, pwm->duty, pwm->period); in tpu_pwm_timer_start()
227 pwm->duty = 0; in tpu_pwm_request()
254 u32 duty; in tpu_pwm_config() local
276 duty = clk_rate / prescalers[prescaler] in tpu_pwm_config()
278 if (duty > period) in tpu_pwm_config()
281 duty = 0; in tpu_pwm_config()
285 "rate %u, prescaler %u, period %u, duty %u\n", in tpu_pwm_config()
286 clk_rate, prescalers[prescaler], period, duty); in tpu_pwm_config()
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| D | pwm-cros-ec.c | 30 * @duty_cycle: cached duty cycle
61 static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) in cros_ec_pwm_set_duty() argument
77 params->duty = duty; in cros_ec_pwm_set_duty()
112 return resp->duty; in cros_ec_pwm_get_duty()
128 * EC doesn't separate the concept of duty cycle and enabled, but in cros_ec_pwm_apply()
151 dev_err(chip->dev, "error getting initial duty: %d\n", ret); in cros_ec_pwm_get_state()
159 * Note that "disabled" and "duty cycle == 0" are treated the same. If in cros_ec_pwm_get_state()
160 * the cached duty cycle is not zero, used the cached duty cycle. This in cros_ec_pwm_get_state()
161 * ensures that the configured duty cycle is kept across a disable and in cros_ec_pwm_get_state()
165 * will be 0 and the actual duty cycle read from the EC is used. in cros_ec_pwm_get_state()
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| D | pwm-sprd.c | 74 u32 val, duty, prescale; in sprd_pwm_get_state() local
98 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_get_state()
101 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate in sprd_pwm_get_state()
109 duty = val & SPRD_PWM_DUTY_MSK; in sprd_pwm_get_state()
110 tmp = (prescale + 1) * NSEC_PER_SEC * duty; in sprd_pwm_get_state()
122 u32 prescale, duty; in sprd_pwm_config() local
128 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_config()
135 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; in sprd_pwm_config()
144 * Note: Writing DUTY triggers the hardware to actually apply the in sprd_pwm_config()
145 * values written to MOD and DUTY to the output, so must keep writing in sprd_pwm_config()
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| D | pwm-atmel-tcb.c | 36 unsigned duty; /* PWM duty expressed in clk cycles */ member
96 tcbpwm->duty = 0; in atmel_tcb_pwm_request()
108 tcbpwm->duty = in atmel_tcb_pwm_request()
111 tcbpwm->duty = in atmel_tcb_pwm_request()
153 * If duty is 0 the timer will be stopped and we have to in atmel_tcb_pwm_disable()
160 if (tcbpwm->duty == 0) in atmel_tcb_pwm_disable()
212 * If duty is 0 the timer will be stopped and we have to in atmel_tcb_pwm_enable()
219 if (tcbpwm->duty == 0) in atmel_tcb_pwm_enable()
245 * If duty is 0 or equal to period there's no need to register in atmel_tcb_pwm_enable()
250 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { in atmel_tcb_pwm_enable()
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| D | pwm-jz4740.c | 105 * Set duty > period. This trick allows the TCU channels in TCU2 mode to in jz4740_pwm_disable()
129 unsigned long period, duty; in jz4740_pwm_apply() local
161 /* Calculate duty value */ in jz4740_pwm_apply()
164 duty = tmp; in jz4740_pwm_apply()
166 if (duty >= period) in jz4740_pwm_apply()
167 duty = period - 1; in jz4740_pwm_apply()
180 /* Set duty */ in jz4740_pwm_apply()
181 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty); in jz4740_pwm_apply()
194 * duty value, then becomes active until the timer reaches the period in jz4740_pwm_apply()
195 * value. In theory, we should then use (period - duty) as the real duty in jz4740_pwm_apply()
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| D | pwm-rockchip.c | 41 unsigned long duty; member
81 tmp = readl_relaxed(pc->base + pc->data->regs.duty); in rockchip_pwm_get_state()
100 unsigned long period, duty; in rockchip_pwm_config() local
107 * Since period and duty cycle registers have a width of 32 in rockchip_pwm_config()
116 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
119 * Lock the period and duty of previous configuration, then in rockchip_pwm_config()
120 * change the duty and period, that would not be effective. in rockchip_pwm_config()
129 writel(duty, pc->base + pc->data->regs.duty); in rockchip_pwm_config()
141 * the configuration of duty, period and polarity in rockchip_pwm_config()
224 .duty = 0x04,
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| D | pwm-iqs620a.c | 9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
62 * The duty cycle generated by the device is calculated as follows: in iqs620_pwm_apply()
67 * (inclusive). Therefore the lowest duty cycle the device can generate in iqs620_pwm_apply()
70 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to in iqs620_pwm_apply()
120 * Since the device cannot generate a 0% duty cycle, requests to do so in iqs620_pwm_get_state()
122 * as disabled with duty cycle equal to that which was in use prior to in iqs620_pwm_get_state()
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| D | pwm-clps711x.c | 45 /* Duty cycle 0..15 max */ in clps711x_get_duty()
67 unsigned int duty; in clps711x_pwm_config() local
72 duty = clps711x_get_duty(pwm, duty_ns); in clps711x_pwm_config()
73 clps711x_pwm_update_val(priv, pwm->hwpwm, duty); in clps711x_pwm_config()
81 unsigned int duty; in clps711x_pwm_enable() local
83 duty = clps711x_get_duty(pwm, pwm_get_duty_cycle(pwm)); in clps711x_pwm_enable()
84 clps711x_pwm_update_val(priv, pwm->hwpwm, duty); in clps711x_pwm_enable()
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| /Linux-v5.10/Documentation/devicetree/bindings/regulator/ |
| D | pwm-regulator.txt | 7 predefined voltage <=> duty-cycle values must be
10 Intermediary duty-cycle values which would normally
19 appropriate duty-cycle values. This allows for a much
22 assumption that a %50 duty-cycle value will cause the
33 - voltage-table: Voltage and Duty-Cycle table consisting of 2 cells
35 Second cell is duty-cycle in percent (%)
38 - pwm-dutycycle-unit: Integer value encoding the duty cycle unit. If not
46 Duty cycle values are expressed in pwm-dutycycle-unit.
71 * Inverted PWM logic, and the duty cycle range is limited
85 /* Voltage Duty-Cycle */
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| /Linux-v5.10/Documentation/hwmon/ |
| D | dme1737.rst | 166 attribute that needs to be set to the maximum attainable RPM (fan at 100% duty-
178 manual mode, the fan speed is set by writing the duty-cycle value to the
180 current duty-cycle as set by the fan controller in the chip. All PWM outputs
191 duty-cycles: full, low, and min. Full is internally hard-wired to 255 (100%)
198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%)
199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm
211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min
214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value,
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| D | vt1211.rst | 181 Each PWM has 4 associated distinct output duty-cycles: full, high, low and
186 thermal thresholds exist that controls both PWMs output duty-cycles. The
194 PWM Auto Point PWM Output Duty-Cycle
196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
215 Thermal Threshold Output Duty-Cycle Output Duty-Cycle
218 - full speed duty-cycle full speed duty-cycle
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| D | lm93.rst | 109 a minimum pulse width of 5 clocks (at 22.5kHz => 6.25% duty cycle), and
110 a maximum pulse width of 80 clocks (at 22.5kHz => 99.88% duty cycle).
115 contains a value controlling the duty cycle for the PWM signal used when
117 indicating minimum duty cycle and 15 indicating maximum.
148 and pwm2 are used to set the manual duty cycle; each is an integer (0-255)
149 where 0 is 0% duty cycle, and 255 is 100%. Note that the duty cycle values
152 PWM mode is disabled, the value of pwm1 and pwm2 indicates the current duty
238 A spin-up cycle occurs when a PWM output is commanded from 0% duty cycle to
239 some value > 0%. The LM93 supports a minimum duty cycle during spin-up. These
241 file has the same representation as other PWM duty cycle values. The
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| /Linux-v5.10/Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.txt | 4 strength increases based on the duty cycle of the enable PWM channel
5 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
8 driven at fixed duty cycle. If available this is can be used to increase
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
64 direction-duty-cycle-ns = <1000000000>;
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| /Linux-v5.10/include/trace/events/ |
| D | clk.h | 189 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
191 TP_ARGS(core, duty),
201 __entry->num = duty->num;
202 __entry->den = duty->den;
211 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
213 TP_ARGS(core, duty)
218 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
220 TP_ARGS(core, duty)
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| /Linux-v5.10/drivers/clk/meson/ |
| D | sclk-div.c | 12 * The duty cycle may also be set for the LR clock variant. The duty cycle
125 struct clk_duty *duty) in sclk_div_set_duty_cycle() argument
131 memcpy(&sclk->cached_duty, duty, sizeof(*duty)); in sclk_div_set_duty_cycle()
139 struct clk_duty *duty) in sclk_div_get_duty_cycle() argument
146 duty->num = 1; in sclk_div_get_duty_cycle()
147 duty->den = 2; in sclk_div_get_duty_cycle()
152 duty->num = hi + 1; in sclk_div_get_duty_cycle()
153 duty->den = sclk->cached_div; in sclk_div_get_duty_cycle()
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| /Linux-v5.10/include/linux/ |
| D | pwm.h | 16 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
19 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
54 * @duty_cycle: PWM duty cycle (in nanoseconds)
125 static inline void pwm_set_duty_cycle(struct pwm_device *pwm, unsigned int duty) in pwm_set_duty_cycle() argument
128 pwm->state.duty_cycle = duty; in pwm_set_duty_cycle()
189 * pwm_get_relative_duty_cycle() - Get a relative duty cycle value
190 * @state: PWM state to extract the duty cycle from
191 * @scale: target scale of the relative duty cycle
193 * This functions converts the absolute duty cycle stored in @state (expressed
199 * duty = pwm_get_relative_duty_cycle(&state, 100);
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| /Linux-v5.10/drivers/leds/ |
| D | leds-pwm.c | 45 unsigned long long duty = led_dat->pwmstate.period; in led_pwm_set() local
47 duty *= brightness; in led_pwm_set()
48 do_div(duty, max); in led_pwm_set()
51 duty = led_dat->pwmstate.period - duty; in led_pwm_set()
53 led_dat->pwmstate.duty_cycle = duty; in led_pwm_set()
54 led_dat->pwmstate.enabled = duty > 0; in led_pwm_set()
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| /Linux-v5.10/drivers/gpu/drm/nouveau/ |
| D | nouveau_led.c | 42 u32 div, duty; in nouveau_led_get_brightness() local
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
48 return duty * LED_FULL / div; in nouveau_led_get_brightness()
62 u32 div, duty; in nouveau_led_set_brightness() local
65 duty = value * div / LED_FULL; in nouveau_led_set_brightness()
73 nvif_wr32(device, 0x61c884, 0xc0000000 | duty); in nouveau_led_set_brightness()
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| /Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/volt/ |
| D | gk104.c | 43 u32 div, duty; in gk104_volt_get() local
46 duty = nvkm_rd32(device, 0x20344); in gk104_volt_get()
48 return bios->base + bios->pwm_range * duty / div; in gk104_volt_get()
56 u32 div, duty; in gk104_volt_set() local
60 duty = DIV_ROUND_UP((uv - bios->base) * div, bios->pwm_range); in gk104_volt_set()
63 nvkm_wr32(device, 0x20344, 0x80000000 | duty); in gk104_volt_set()
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| /Linux-v5.10/Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 71 or decreased by modulating the duty cycle of the idle injection.
86 duty cycle 25%
90 the duty cycle percentage. When no mitigation is happening the cooling
91 device state is zero, meaning the duty cycle is 0%.
94 starting state is selected. With a fixed idle duration and the duty
98 The governor will change the cooling device state thus the duty cycle
114 duty cycle 33%
128 duty cycle 50%
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