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/Linux-v5.15/include/linux/soc/qcom/
Dllcc-qcom.h39 * @slice_id: llcc slice id
40 * @slice_size: Size allocated for the llcc slice
48 * struct llcc_edac_reg_data - llcc edac registers data for each error type
72 * struct llcc_drv_data - Data associated with the llcc driver
73 * @regmap: regmap associated with the llcc device
74 * @bcast_regmap: regmap associated with llcc broadcast offset
79 * @num_banks: Number of llcc banks
82 * @ecc_irq: interrupt for llcc cache error detection and reporting
83 * @major_version: Indicates the LLCC major version
101 * llcc_slice_getd - get llcc slice descriptor
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/msm/
Dqcom,llcc.yaml4 $id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
24 - qcom,sc7180-llcc
25 - qcom,sc7280-llcc
26 - qcom,sdm845-llcc
27 - qcom,sm8150-llcc
28 - qcom,sm8250-llcc
32 - description: LLCC base register region
33 - description: LLCC broadcast base register region
56 compatible = "qcom,sdm845-llcc";
/Linux-v5.15/drivers/soc/qcom/
Dllcc-qcom.c20 #include <linux/soc/qcom/llcc-qcom.h>
59 * struct llcc_slice_config - Data associated with the llcc slice
61 * @slice_id: llcc slice id for each client
75 * When configured to 0 all ways in llcc are probed.
219 * llcc_slice_getd - get llcc slice descriptor
222 * A pointer to llcc slice descriptor will be returned on success and
256 * llcc_slice_putd - llcc slice descritpor
257 * @desc: Pointer to llcc slice descriptor
301 * llcc_slice_activate - Activate the llcc slice
302 * @desc: Pointer to llcc slice descriptor
[all …]
DKconfig64 tristate "Qualcomm Technologies, Inc. LLCC driver"
68 Last Level Cache Controller(LLCC) driver for platforms such as,
69 SDM845. This provides interfaces to clients that use the LLCC.
70 Say yes here to enable LLCC slice driver.
DMakefile25 obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
/Linux-v5.15/drivers/edac/
Dqcom_edac.c12 #include <linux/soc/qcom/llcc-qcom.h>
265 "LLCC Data RAM correctable Error"); in dump_syn_reg()
269 "LLCC Data RAM uncorrectable Error"); in dump_syn_reg()
273 "LLCC Tag RAM correctable Error"); in dump_syn_reg()
277 "LLCC Tag RAM uncorrectable Error"); in dump_syn_reg()
348 edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank", in qcom_llcc_edac_probe()
359 edev_ctl->ctl_name = "llcc"; in qcom_llcc_edac_probe()
DKconfig513 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
/Linux-v5.15/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_core_perf.h20 * @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus
21 * @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus
Ddpu_crtc.h184 * @bw_split_vote : true if bw controlled by llcc/dram bw properties
Ddpu_hw_catalog.h677 * @min_llcc_ib minimum llcc ib vote in kbps
/Linux-v5.15/drivers/net/ethernet/sun/
Dcassini.h2200 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2298 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2378 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2434 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
/Linux-v5.15/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.c14 #include <linux/soc/qcom/llcc-qcom.h>
/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsc7280.dtsi1336 compatible = "qcom,sc7280-llcc";
Dsm8150.dtsi1624 compatible = "qcom,sm8150-llcc";
Dsc7180.dtsi2732 compatible = "qcom,sc7180-llcc";
Dsm8250.dtsi2457 compatible = "qcom,sm8250-llcc";
Dsdm845.dtsi1970 compatible = "qcom,sdm845-llcc";