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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml23 0x0100 FMREG
40 0x0100 FMREG
49 0x1100 FMREG
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
62 added on V2; the FMREG bank for slew rate calibration is not used anymore
Dmediatek,xsphy.yaml21 0x0100 FMREG
24 0x1100 FMREG
/Linux-v5.15/drivers/phy/mediatek/
Dphy-mtk-tphy.c315 void __iomem *fmreg; member
361 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate() local
382 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
384 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
387 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
393 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
396 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
398 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
401 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, in hs_slew_rate_calibrate()
404 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); in hs_slew_rate_calibrate()
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