Lines Matching full:fmreg
315 void __iomem *fmreg; member
361 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate() local
382 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
384 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
387 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
393 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
396 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
398 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
401 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, in hs_slew_rate_calibrate()
404 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); in hs_slew_rate_calibrate()
407 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
409 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
412 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
414 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
867 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; in phy_v1_banks_init()
895 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; in phy_v2_banks_init()