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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
22 * Adjustable tx de-emphasis (FFE)
31 The SERDES6G is a high-speed SERDES interface, which can operate at
34 * 100 Mbps (100BASE-FX)
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
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/Linux-v5.15/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
36 #define MDIO_DEVS1 5 /* Devices in package */
38 #define MDIO_CTRL2 7 /* 10G control 2 */
39 #define MDIO_STAT2 8 /* 10G status 2 */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
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/Linux-v5.15/drivers/net/phy/
Daquantia_main.c1 // SPDX-License-Identifier: GPL-2.0
48 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
167 int len_l = min(stat->size, 16); in aqr107_get_stat()
168 int len_h = stat->size - len_l; in aqr107_get_stat()
172 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); in aqr107_get_stat()
176 ret = val & GENMASK(len_l - 1, 0); in aqr107_get_stat()
178 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); in aqr107_get_stat()
182 ret += (val & GENMASK(len_h - 1, 0)) << 16; in aqr107_get_stat()
191 struct aqr107_priv *priv = phydev->priv; in aqr107_get_stats()
201 priv->sgmii_stats[i] += val; in aqr107_get_stats()
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Dmxl-gpy.c1 // SPDX-License-Identifier: GPL-2.0+
44 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
45 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
46 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
101 if (!phydev->is_c45) { in gpy_probe()
156 phydev->speed = SPEED_2500; in gpy_2500basex_chk()
157 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in gpy_2500basex_chk()
183 if (phydev->autoneg == AUTONEG_DISABLE) { in gpy_config_aneg()
187 return phydev->duplex != DUPLEX_FULL in gpy_config_aneg()
198 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in gpy_config_aneg()
[all …]
Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
87 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
91 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
92 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
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Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
40 * struct phylink - internal data type for phylink
57 u8 link_port; /* The current non-phy ethtool port */
86 if ((pl)->config->type == PHYLINK_NETDEV) \
87 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
88 else if ((pl)->config->type == PHYLINK_DEV) \
89 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
101 if ((pl)->config->type == PHYLINK_NETDEV) \
102 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \
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/Linux-v5.15/drivers/net/pcs/
Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/pcs/pcs-xpcs.h>
14 #include "pcs-xpcs.h"
139 const struct xpcs_compat *compat = &id->compat[i]; in xpcs_find_compat()
141 for (j = 0; j < compat->num_interfaces; j++) in xpcs_find_compat()
142 if (compat->interface[j] == interface) in xpcs_find_compat()
153 compat = xpcs_find_compat(xpcs->id, interface); in xpcs_get_an_mode()
155 return -ENODEV; in xpcs_get_an_mode()
157 return compat->an_mode; in xpcs_get_an_mode()
166 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()
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/Linux-v5.15/include/linux/
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
73 * Set phydev->irq to PHY_POLL if interrupts are not supported,
77 #define PHY_POLL -1
78 #define PHY_MAC_INTERRUPT -2
86 * enum phy_interface_t - Interface Mode definitions
88 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
90 * @PHY_INTERFACE_MODE_MII: Median-independent interface
91 * @PHY_INTERFACE_MODE_GMII: Gigabit median-independent interface
92 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
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