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/Linux-v5.15/Documentation/admin-guide/media/
Dgspca-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - gspca_main: main driver
9 - gspca\_\ *driver*: subdriver module with *driver* as follows
19 spca501 040a:0002 Kodak DVC-325
24 spca500 041e:400a Creative PC-CAM 300
25 sunplus 041e:400b Creative PC-CAM 600
26 sunplus 041e:4012 PC-Cam350
41 sq930x 041e:4038 Creative Joy-IT
69 sn9c20x 0458:704c Genius i-Look 1321
70 sn9c20x 045e:00f4 LifeCam VX-6000 (SN9C20x + OV9650)
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/net/
Dbroadcom-bcm87xx.txt5 "ethernet-phy-ieee802.3-c45"
9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
18 ethernet-phy@5 {
20 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
21 interrupt-parent = <&gpio>;
28 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
16 - nvmem-cell-names: Should be "address"
[all …]
Dsff,sfp.txt1 Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
6 - compatible : must be one of
10 - i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
15 - mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
19 - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
28 - rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
32 - rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
36 - maximum-power-milliwatt : Maximum module power consumption
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2018-2020 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2019-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
27 stdout-path = "serial0:115200n8";
40 mmc-hs200-1_8v;
41 sd-uhs-sdr104;
42 sd-uhs-sdr50;
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
86 3 0 0xf 0xffdf0000 0x00008000>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
[all …]
Db4860qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4860si-pre.dtsi"
50 board-control@3,0 {
51 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
58 phy-handle = <&phy_sgmii_1e>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_1f>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&phy_xaui_slot1>;
69 phy-connection-type = "xgmii";
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
Dt1024rdb.dts35 /include/ "t102xsi-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
53 bman_fbpr: bman-fbpr {
58 qman_fqd: qman-fqd {
63 qman_pfdr: qman-pfdr {
[all …]
Dp3041ds.dts4 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
35 /include/ "p3041si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
Dp5020ds.dts4 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5020si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fqd {
[all …]
/Linux-v5.15/arch/arm64/boot/dts/marvell/
Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Double-shot";
12 compatible = "marvell,armada8040-mcbin-doubleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
/Linux-v5.15/drivers/net/phy/
Dbcm87xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2012 Cavium, Inc.
22 * broadcom,c45-reg-init property stored in the of_node for the phydev.
24 * broadcom,c45-reg-init = <devid reg mask value>,...;
28 * devid: which sub-device to use.
30 * mask: if non-zero, ANDed with existing register value.
40 if (!phydev->mdio.dev.of_node) in bcm87xx_of_reg_init()
43 paddr = of_get_property(phydev->mdio.dev.of_node, in bcm87xx_of_reg_init()
44 "broadcom,c45-reg-init", &len); in bcm87xx_of_reg_init()
52 while (paddr + 3 < paddr_end) { in bcm87xx_of_reg_init()
[all …]
/Linux-v5.15/drivers/net/mdio/
Dmdio-cavium.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009-2016 Cavium, Inc.
11 #include "mdio-cavium.h"
18 if (m == p->mode) in cavium_mdiobus_set_mode()
21 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
22 smi_clk.s.mode = (m == C45) ? 1 : 0; in cavium_mdiobus_set_mode()
24 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
25 p->mode = m; in cavium_mdiobus_set_mode()
35 cavium_mdiobus_set_mode(p, C45); in cavium_mdiobus_c45_addr()
39 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
[all …]
Dmdio-cavium.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2009-2016 Cavium, Inc.
9 C45 enumerator
35 OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
52 OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
54 OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
111 #include <linux/io-64-nonatomic-lo-hi.h>
Dof_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * ethernet-phy-idAAAA.BBBB */
66 device_set_node(&mdiodev->dev, fwnode); in of_mdiobus_register_device()
76 dev_dbg(&mdio->dev, "registered mdio device %pOFn at address %i\n", in of_mdiobus_register_device()
88 { .compatible = "brcm,40nm-ephy" },
98 { .compatible = "moxa,moxart-rtl8201cp", },
104 * o Compatible string of "ethernet-phy-idX.X"
105 * o Compatible string of "ethernet-phy-ieee802.3-c45"
106 * o Compatible string of "ethernet-phy-ieee802.3-c22"
117 if (of_get_phy_id(child, &phy_id) != -EINVAL) in of_mdiobus_child_is_phy()
[all …]
Dfwnode_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
28 if (err == -ENOENT) in fwnode_find_mii_timestamper()
34 return ERR_PTR(-EINVAL); in fwnode_find_mii_timestamper()
46 if (rc == -EPROBE_DEFER) in fwnode_mdiobus_phy_device_register()
50 phy->irq = rc; in fwnode_mdiobus_phy_device_register()
51 mdio->irq[addr] = rc; in fwnode_mdiobus_phy_device_register()
53 phy->irq = mdio->irq[addr]; in fwnode_mdiobus_phy_device_register()
56 if (fwnode_property_read_bool(child, "broken-turn-around")) in fwnode_mdiobus_phy_device_register()
57 mdio->phy_ignore_ta_mask |= 1 << addr; in fwnode_mdiobus_phy_device_register()
59 fwnode_property_read_u32(child, "reset-assert-us", in fwnode_mdiobus_phy_device_register()
[all …]
/Linux-v5.15/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
31 unsigned long fin_time = jiffies + 3 * HZ; /* 3 seconds */ in sxgbe_mdio_busy_wait()
39 return -EBUSY; in sxgbe_mdio_busy_wait()
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
49 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
60 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
70 writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG); in sxgbe_mdio_c22()
74 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
82 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access()
85 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access()
[all …]
/Linux-v5.15/drivers/platform/x86/intel/int1092/
Dintel_sar.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define MAX_REGULATORY 3
13 #define SAR_DSM_UUID "82737E72-3A33-4C45-A9C7-57C0411A5F13"
19 * Structure wwan_device_mode_info - device mode information
35 * Structure wwan_device_mode_configuration - device configuration
49 * Structure wwan_supported_info - userspace datastore
64 * Structure wwan_sar_context - context of SAR

12