Home
last modified time | relevance | path

Searched +full:0 +full:xf00 (Results 1 – 25 of 275) sorted by relevance

1234567891011

/Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/
Dmsi.txt86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xb 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
/Linux-v5.4/drivers/pinctrl/mediatek/
Dpinctrl-mt2701.c39 /* 0E4E8SR 4/8/12/16 */
41 /* 0E2E4SR 2/4/6/8 */
44 MTK_DRV_GRP(2, 16, 0, 2, 2)
48 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
54 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
/Linux-v5.4/drivers/regulator/
Dmt6358-regulator.c16 #define MT6358_BUCK_MODE_AUTO 0
57 .enable_mask = BIT(0), \
61 .qi = BIT(0), \
112 .enable_mask = BIT(0), \
118 .qi = BIT(0), \
141 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
145 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
149 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
153 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
204 0, 12,
[all …]
/Linux-v5.4/drivers/net/ethernet/moxa/
Dmoxart_ether.h18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
[all …]
/Linux-v5.4/arch/arm/mm/
Dtlb-v4wbi.S34 mov r3, #0
35 mcr p15, 0, r3, c7, c10, 4 @ drain WB
37 bic r0, r0, #0x0ff
38 bic r0, r0, #0xf00
40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
48 mov r3, #0
49 mcr p15, 0, r3, c7, c10, 4 @ drain WB
50 bic r0, r0, #0x0ff
51 bic r0, r0, #0xf00
[all …]
Dtlb-fa.S39 mov r3, #0
40 mcr p15, 0, r3, c7, c10, 4 @ drain WB
41 bic r0, r0, #0x0ff
42 bic r0, r0, #0xf00
43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
52 mov r3, #0
53 mcr p15, 0, r3, c7, c10, 4 @ drain WB
54 bic r0, r0, #0x0ff
55 bic r0, r0, #0xf00
[all …]
Dtlb-v4wb.S36 mcr p15, 0, r3, c7, c10, 4 @ drain WB
38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
39 bic r0, r0, #0x0ff
40 bic r0, r0, #0xf00
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
57 mov r3, #0
58 mcr p15, 0, r3, c7, c10, 4 @ drain WB
59 bic r0, r0, #0x0ff
60 bic r0, r0, #0xf00
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
[all …]
/Linux-v5.4/drivers/media/pci/ddbridge/
Dddbridge-hw.c25 .base = 0x200,
26 .num = 0x08,
27 .size = 0x10,
31 .base = 0x280,
32 .num = 0x08,
33 .size = 0x10,
37 .base = 0x300,
38 .num = 0x08,
39 .size = 0x10,
43 .base = 0x2000,
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/Linux-v5.4/arch/microblaze/pci/
Dindirect_pci.c23 u8 cfg_type = 0; in indirect_read_config()
29 if (devfn != 0) in indirect_read_config()
41 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in indirect_read_config()
43 reg = offset & 0xfc; /* Only 3 bits for function */ in indirect_read_config()
46 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_read_config()
49 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_read_config()
77 u8 cfg_type = 0; in indirect_write_config()
83 if (devfn != 0) in indirect_write_config()
95 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in indirect_write_config()
97 reg = offset & 0xfc; in indirect_write_config()
[all …]
/Linux-v5.4/drivers/soc/qcom/
Dllcc-sdm845.c30 * When configured to 0 all ways in llcc are probed.
54 SCT_ENTRY(LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1),
55 SCT_ENTRY(LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
56 SCT_ENTRY(LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
57 SCT_ENTRY(LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0),
58 SCT_ENTRY(LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
59 SCT_ENTRY(LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
60 SCT_ENTRY(LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0),
61 SCT_ENTRY(LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
62 SCT_ENTRY(LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
[all …]
/Linux-v5.4/arch/powerpc/sysdev/
Dindirect_pci.c24 u8 cfg_type = 0; in __indirect_read_config()
30 if (devfn != 0) in __indirect_read_config()
46 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in __indirect_read_config()
48 reg = offset & 0xfc; in __indirect_read_config()
51 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in __indirect_read_config()
54 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in __indirect_read_config()
90 u8 cfg_type = 0; in indirect_write_config()
96 if (devfn != 0) in indirect_write_config()
112 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in indirect_write_config()
114 reg = offset & 0xfc; in indirect_write_config()
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dnxp,lpc3220-usb-clk.txt15 ranges = <0x0 0x31020000 0x00001000>;
19 reg = <0xf00 0x100>;
/Linux-v5.4/Documentation/devicetree/bindings/sound/
Dmtk-btcvsd-snd.txt19 reg=<0 0x18000000 0 0x1000>,
20 <0 0x18080000 0 0x8000>;
23 mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>;
/Linux-v5.4/drivers/hwtracing/coresight/
Dcoresight-priv.h16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
20 #define CORESIGHT_ITCTRL 0xf00
21 #define CORESIGHT_CLAIMSET 0xfa0
22 #define CORESIGHT_CLAIMCLR 0xfa4
23 #define CORESIGHT_LAR 0xfb0
24 #define CORESIGHT_LSR 0xfb4
25 #define CORESIGHT_AUTHSTATUS 0xfb8
26 #define CORESIGHT_DEVID 0xfc8
27 #define CORESIGHT_DEVTYPE 0xfcc
[all …]
Dcoresight-etm4x.h15 * 0x000 - 0x2FC: Trace registers
16 * 0x300 - 0x314: Management registers
17 * 0x318 - 0xEFC: Trace registers
18 * 0xF00: Management registers
19 * 0xFA0 - 0xFA4: Trace registers
20 * 0xFA8 - 0xFFC: Management registers
22 /* Trace registers (0x000-0x2FC) */
24 #define TRCPRGCTLR 0x004
25 #define TRCPROCSELR 0x008
26 #define TRCSTATR 0x00C
[all …]
/Linux-v5.4/tools/perf/arch/powerpc/util/
Dbook3s_hv_exits.h10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
/Linux-v5.4/arch/powerpc/kvm/
Dtrace_book3s.h10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
/Linux-v5.4/arch/arm/include/debug/
Dexynos.S9 #define S3C_ADDR_BASE 0xF6000000
10 #define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
11 #define EXYNOS4_PA_UART 0x13800000
12 #define EXYNOS5_PA_UART 0x12C00000
21 mrc p15, 0, \tmp, c0, c0, 0
22 and \tmp, \tmp, #0xf0
23 teq \tmp, #0xf0 @@ A15
25 mrc p15, 0, \tmp, c0, c0, 5
26 and \tmp, \tmp, #0xf00
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]

1234567891011