Lines Matching +full:0 +full:xf00
15 * 0x000 - 0x2FC: Trace registers
16 * 0x300 - 0x314: Management registers
17 * 0x318 - 0xEFC: Trace registers
18 * 0xF00: Management registers
19 * 0xFA0 - 0xFA4: Trace registers
20 * 0xFA8 - 0xFFC: Management registers
22 /* Trace registers (0x000-0x2FC) */
24 #define TRCPRGCTLR 0x004
25 #define TRCPROCSELR 0x008
26 #define TRCSTATR 0x00C
27 #define TRCCONFIGR 0x010
28 #define TRCAUXCTLR 0x018
29 #define TRCEVENTCTL0R 0x020
30 #define TRCEVENTCTL1R 0x024
31 #define TRCSTALLCTLR 0x02C
32 #define TRCTSCTLR 0x030
33 #define TRCSYNCPR 0x034
34 #define TRCCCCTLR 0x038
35 #define TRCBBCTLR 0x03C
36 #define TRCTRACEIDR 0x040
37 #define TRCQCTLR 0x044
39 #define TRCVICTLR 0x080
40 #define TRCVIIECTLR 0x084
41 #define TRCVISSCTLR 0x088
42 #define TRCVIPCSSCTLR 0x08C
43 #define TRCVDCTLR 0x0A0
44 #define TRCVDSACCTLR 0x0A4
45 #define TRCVDARCCTLR 0x0A8
47 #define TRCSEQEVRn(n) (0x100 + (n * 4))
48 #define TRCSEQRSTEVR 0x118
49 #define TRCSEQSTR 0x11C
50 #define TRCEXTINSELR 0x120
51 #define TRCCNTRLDVRn(n) (0x140 + (n * 4))
52 #define TRCCNTCTLRn(n) (0x150 + (n * 4))
53 #define TRCCNTVRn(n) (0x160 + (n * 4))
55 #define TRCIDR8 0x180
56 #define TRCIDR9 0x184
57 #define TRCIDR10 0x188
58 #define TRCIDR11 0x18C
59 #define TRCIDR12 0x190
60 #define TRCIDR13 0x194
61 #define TRCIMSPEC0 0x1C0
62 #define TRCIMSPECn(n) (0x1C0 + (n * 4))
63 #define TRCIDR0 0x1E0
64 #define TRCIDR1 0x1E4
65 #define TRCIDR2 0x1E8
66 #define TRCIDR3 0x1EC
67 #define TRCIDR4 0x1F0
68 #define TRCIDR5 0x1F4
69 #define TRCIDR6 0x1F8
70 #define TRCIDR7 0x1FC
72 #define TRCRSCTLRn(n) (0x200 + (n * 4))
74 #define TRCSSCCRn(n) (0x280 + (n * 4))
75 #define TRCSSCSRn(n) (0x2A0 + (n * 4))
76 #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
77 /* Management registers (0x300-0x314) */
78 #define TRCOSLAR 0x300
79 #define TRCOSLSR 0x304
80 #define TRCPDCR 0x310
81 #define TRCPDSR 0x314
82 /* Trace registers (0x318-0xEFC) */
84 #define TRCACVRn(n) (0x400 + (n * 8))
85 #define TRCACATRn(n) (0x480 + (n * 8))
86 #define TRCDVCVRn(n) (0x500 + (n * 16))
87 #define TRCDVCMRn(n) (0x580 + (n * 16))
88 #define TRCCIDCVRn(n) (0x600 + (n * 8))
89 #define TRCVMIDCVRn(n) (0x640 + (n * 8))
90 #define TRCCIDCCTLR0 0x680
91 #define TRCCIDCCTLR1 0x684
92 #define TRCVMIDCCTLR0 0x688
93 #define TRCVMIDCCTLR1 0x68C
94 /* Management register (0xF00) */
96 #define TRCITCTRL 0xF00
97 /* Trace registers (0xFA0-0xFA4) */
99 #define TRCCLAIMSET 0xFA0
100 #define TRCCLAIMCLR 0xFA4
101 /* Management registers (0xFA8-0xFFC) */
102 #define TRCDEVAFF0 0xFA8
103 #define TRCDEVAFF1 0xFAC
104 #define TRCLAR 0xFB0
105 #define TRCLSR 0xFB4
106 #define TRCAUTHSTATUS 0xFB8
107 #define TRCDEVARCH 0xFBC
108 #define TRCDEVID 0xFC8
109 #define TRCDEVTYPE 0xFCC
110 #define TRCPIDR4 0xFD0
111 #define TRCPIDR5 0xFD4
112 #define TRCPIDR6 0xFD8
113 #define TRCPIDR7 0xFDC
114 #define TRCPIDR0 0xFE0
115 #define TRCPIDR1 0xFE4
116 #define TRCPIDR2 0xFE8
117 #define TRCPIDR3 0xFEC
118 #define TRCCIDR0 0xFF0
119 #define TRCCIDR1 0xFF4
120 #define TRCCIDR2 0xFF8
121 #define TRCCIDR3 0xFFC
139 #define ETM_ARCH_V4 0x40
140 #define ETMv4_SYNC_MASK 0x1F
141 #define ETM_CYC_THRESHOLD_MASK 0xFFF
142 #define ETM_CYC_THRESHOLD_DEFAULT 0x100
143 #define ETMv4_EVENT_MASK 0xFF
144 #define ETM_CNTR_MAX_VAL 0xFFFF
145 #define ETM_TRACEID_MASK 0x3f
148 #define ETM_MODE_EXCLUDE BIT(0)
173 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \
177 #define TRCSTATR_IDLE_BIT 0
178 #define ETM_DEFAULT_ADDR_COMP 0
216 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
233 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
237 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
296 * as found in ETMIDR4 0-3.