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/Linux-v5.10/arch/arm/mach-tegra/
Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/Linux-v5.10/arch/arm/include/debug/
Dtegra.S21 #define TEGRA_CLK_RESET_BASE 0x60006000
22 #define TEGRA_APB_MISC_BASE 0x70000000
23 #define TEGRA_UARTA_BASE 0x70006000
24 #define TEGRA_UARTB_BASE 0x70006040
25 #define TEGRA_UARTC_BASE 0x70006200
26 #define TEGRA_UARTD_BASE 0x70006300
27 #define TEGRA_UARTE_BASE 0x70006400
28 #define TEGRA_PMC_BASE 0x7000e400
30 #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
31 #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml89 enum: [0, 1, 2]
92 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
158 Defaults to 0. Valid values are described in section 12.5.2
186 3d0 3D Graphics 0 Tegra30
230 const: 0
231 description: Must be 0.
327 reg = <0x7000e400 0x400>;
333 nvidia,suspend-mode = <0>;
334 nvidia,cpu-pwr-good-time = <0>;
335 nvidia,cpu-pwr-off-time = <0>;
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x50000000 0x00028000>;
35 ranges = <0x54000000 0x54000000 0x01000000>;
39 reg = <0x54140000 0x00040000>;
50 reg = <0x54180000 0x00040000>;
60 reg = <0x54200000 0x00040000>;
70 nvidia,head = <0>;
79 reg = <0x54240000 0x00040000>;
98 reg = <0x54280000 0x00040000>;
110 reg = <0x54300000 0x00040000>;
[all …]
Dtegra20.dtsi15 memory@0 {
17 reg = <0 0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00024000>;
47 ranges = <0x54000000 0x54000000 0x04000000>;
51 reg = <0x54040000 0x00040000>;
60 reg = <0x54080000 0x00040000>;
69 reg = <0x540c0000 0x00040000>;
[all …]
Dtegra30.dtsi17 reg = <0x80000000 0x0>;
23 reg = <0x00003000 0x00000800>, /* PADS registers */
24 <0x00003800 0x00000200>, /* AFI registers */
25 <0x10000000 0x10000000>; /* configuration space */
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35 bus-range = <0x00 0xff>;
39 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
40 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
41 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
[all …]
Dtegra124.dtsi19 reg = <0x0 0x80000000 0x0 0x0>;
25 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
26 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
27 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
34 interrupt-map-mask = <0 0 0 0>;
35 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
37 bus-range = <0x00 0xff>;
41 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
42 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
43 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
/Linux-v5.10/arch/arm64/boot/dts/nvidia/
Dtegra132.dtsi20 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
21 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
22 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
37 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
38 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
39 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/Linux-v5.10/drivers/soc/tegra/
Dpmc.c57 #define PMC_CNTRL 0x0
68 #define PMC_WAKE_MASK 0x0c
69 #define PMC_WAKE_LEVEL 0x10
70 #define PMC_WAKE_STATUS 0x14
71 #define PMC_SW_WAKE_STATUS 0x18
72 #define PMC_DPD_PADS_ORIDE 0x1c
75 #define DPD_SAMPLE 0x020
76 #define DPD_SAMPLE_ENABLE BIT(0)
77 #define DPD_SAMPLE_DISABLE (0 << 0)
79 #define PWRGATE_TOGGLE 0x30
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