Lines Matching +full:0 +full:x7000e400
20 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
21 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
22 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
37 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
38 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
39 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
40 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
53 pci@1,0 {
55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
57 bus-range = <0x00 0xff>;
67 pci@2,0 {
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
71 bus-range = <0x00 0xff>;
85 reg = <0x0 0x50000000 0x0 0x00034000>;
97 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
101 reg = <0x0 0x54200000 0x0 0x00040000>;
110 nvidia,head = <0>;
115 reg = <0x0 0x54240000 0x0 0x00040000>;
129 reg = <0x0 0x54280000 0x0 0x00040000>;
141 reg = <0x0 0x54540000 0x0 0x00040000>;
156 reg = <0x0 0x545c0000 0x0 0x00040000>;
167 #size-cells = <0>;
176 reg = <0x0 0x50041000 0x0 0x1000>,
177 <0x0 0x50042000 0x0 0x2000>,
178 <0x0 0x50044000 0x0 0x2000>,
179 <0x0 0x50046000 0x0 0x2000>;
187 reg = <0x0 0x57000000 0x0 0x01000000>,
188 <0x0 0x58000000 0x0 0x01000000>;
202 reg = <0x0 0x60004000 0x0 0x100>,
203 <0x0 0x60004100 0x0 0x100>,
204 <0x0 0x60004200 0x0 0x100>,
205 <0x0 0x60004300 0x0 0x100>,
206 <0x0 0x60004400 0x0 0x100>;
214 reg = <0x0 0x60005000 0x0 0x400>;
215 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
227 reg = <0x0 0x60006000 0x0 0x1000>;
235 reg = <0x0 0x60007000 0x0 0x1000>;
240 reg = <0x0 0x6000c800 0x0 0x400>;
251 reg = <0x0 0x6000d000 0x0 0x1000>;
268 reg = <0x0 0x60020000 0x0 0x1400>;
310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
318 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
331 reg = <0x0 0x70006000 0x0 0x40>;
345 reg = <0x0 0x70006040 0x0 0x40>;
359 reg = <0x0 0x70006200 0x0 0x40>;
373 reg = <0x0 0x70006300 0x0 0x40>;
387 reg = <0x0 0x7000a000 0x0 0x100>;
398 reg = <0x0 0x7000c000 0x0 0x100>;
401 #size-cells = <0>;
413 reg = <0x0 0x7000c400 0x0 0x100>;
416 #size-cells = <0>;
428 reg = <0x0 0x7000c500 0x0 0x100>;
431 #size-cells = <0>;
443 reg = <0x0 0x7000c700 0x0 0x100>;
446 #size-cells = <0>;
458 reg = <0x0 0x7000d000 0x0 0x100>;
461 #size-cells = <0>;
473 reg = <0x0 0x7000d100 0x0 0x100>;
476 #size-cells = <0>;
488 reg = <0x0 0x7000d400 0x0 0x200>;
491 #size-cells = <0>;
503 reg = <0x0 0x7000d600 0x0 0x200>;
506 #size-cells = <0>;
518 reg = <0x0 0x7000d800 0x0 0x200>;
521 #size-cells = <0>;
533 reg = <0x0 0x7000da00 0x0 0x200>;
536 #size-cells = <0>;
548 reg = <0x0 0x7000dc00 0x0 0x200>;
551 #size-cells = <0>;
563 reg = <0x0 0x7000de00 0x0 0x200>;
566 #size-cells = <0>;
578 reg = <0x0 0x7000e000 0x0 0x100>;
586 reg = <0x0 0x7000e400 0x0 0x400>;
594 reg = <0x0 0x7000f800 0x0 0x400>;
603 reg = <0x0 0x70019000 0x0 0x1000>;
614 reg = <0x0 0x7001b000 0x0 0x1000>;
623 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
624 <0x0 0x70020000 0x0 0x7000>; /* SATA */
641 reg = <0x0 0x70030000 0x0 0x10000>;
656 reg = <0x0 0x70090000 0x0 0x8000>,
657 <0x0 0x70098000 0x0 0x1000>,
658 <0x0 0x70099000 0x0 0x1000>;
692 reg = <0x0 0x7009f000 0x0 0x1000>;
701 usb2-0 {
703 #phy-cells = <0>;
708 #phy-cells = <0>;
713 #phy-cells = <0>;
722 ulpi-0 {
724 #phy-cells = <0>;
733 hsic-0 {
735 #phy-cells = <0>;
740 #phy-cells = <0>;
749 pcie-0 {
751 #phy-cells = <0>;
756 #phy-cells = <0>;
761 #phy-cells = <0>;
766 #phy-cells = <0>;
771 #phy-cells = <0>;
780 sata-0 {
782 #phy-cells = <0>;
789 usb2-0 {
801 hsic-0 {
809 usb3-0 {
821 reg = <0x0 0x700b0000 0x0 0x200>;
832 reg = <0x0 0x700b0200 0x0 0x200>;
843 reg = <0x0 0x700b0400 0x0 0x200>;
854 reg = <0x0 0x700b0600 0x0 0x200>;
865 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
866 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
889 polling-delay = <0>;
916 polling-delay-passive = <0>;
917 polling-delay = <0>;
939 polling-delay = <0>;
966 polling-delay-passive = <0>;
967 polling-delay = <0>;
991 reg = <0x0 0x70300000 0x0 0x200>,
992 <0x0 0x70300800 0x0 0x800>,
993 <0x0 0x70300200 0x0 0x600>;
1043 reg = <0x0 0x70301000 0x0 0x100>;
1054 reg = <0x0 0x70301100 0x0 0x100>;
1065 reg = <0x0 0x70301200 0x0 0x100>;
1076 reg = <0x0 0x70301300 0x0 0x100>;
1087 reg = <0x0 0x70301400 0x0 0x100>;
1099 reg = <0x0 0x7d000000 0x0 0x4000>;
1112 reg = <0x0 0x7d000000 0x0 0x4000>,
1113 <0x0 0x7d000000 0x0 0x4000>;
1121 #phy-cells = <0>;
1122 nvidia,hssync-start-delay = <0>;
1127 nvidia,xcvr-lsfslew = <0>;
1138 reg = <0x0 0x7d004000 0x0 0x4000>;
1151 reg = <0x0 0x7d004000 0x0 0x4000>,
1152 <0x0 0x7d000000 0x0 0x4000>;
1160 #phy-cells = <0>;
1161 nvidia,hssync-start-delay = <0>;
1166 nvidia,xcvr-lsfslew = <0>;
1176 reg = <0x0 0x7d008000 0x0 0x4000>;
1189 reg = <0x0 0x7d008000 0x0 0x4000>,
1190 <0x0 0x7d000000 0x0 0x4000>;
1198 #phy-cells = <0>;
1199 nvidia,hssync-start-delay = <0>;
1204 nvidia,xcvr-lsfslew = <0>;
1214 #size-cells = <0>;
1216 cpu@0 {
1219 reg = <0>;