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/Linux-v5.15/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/Linux-v5.15/arch/arm/include/asm/hardware/
Dcache-aurora-l2.h17 #define AURORA_SYNC_REG 0x700
18 #define AURORA_RANGE_BASE_ADDR_REG 0x720
19 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
20 #define AURORA_INVAL_RANGE_REG 0x774
21 #define AURORA_CLEAN_RANGE_REG 0x7b4
22 #define AURORA_FLUSH_RANGE_REG 0x7f4
26 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
28 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
37 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
39 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
[all …]
/Linux-v5.15/include/linux/soc/mmp/
Dcputype.h12 * PXA168 S0 0x56158400 0x0000C910
13 * PXA168 A0 0x56158400 0x00A0A168
14 * PXA910 Y1 0x56158400 0x00F2C920
15 * PXA910 A0 0x56158400 0x00F2C910
16 * PXA910 A1 0x56158400 0x00A0C910
17 * PXA920 Y0 0x56158400 0x00F2C920
18 * PXA920 A0 0x56158400 0x00A0C920
19 * PXA920 A1 0x56158400 0x00A1C920
20 * MMP2 Z0 0x560f5811 0x00F00410
21 * MMP2 Z1 0x560f5811 0x00E00410
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Drenesas,emev2-smu.yaml28 const: 0
61 const: 0
92 const: 0
112 reg = <0xe0110000 0x10000>;
114 #size-cells = <0>;
119 #clock-cells = <0>;
126 #clock-cells = <0>;
128 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
130 reg = <0x610 0>;
132 #clock-cells = <0>;
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
Demev2.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0>;
49 reg = <0xe0028000 0x1000>,
50 <0xe0020000 0x0100>;
62 reg = <0xe0110000 0x10000>;
64 #size-cells = <0>;
69 #clock-cells = <0>;
71 iic0_sclkdiv: iic0_sclkdiv@624,0 {
73 reg = <0x624 0>;
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgv100.c32 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); in gv100_gr_trap_sm()
33 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); in gv100_gr_trap_sm()
38 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); in gv100_gr_trap_sm()
44 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); in gv100_gr_trap_sm()
45 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); in gv100_gr_trap_sm()
51 gv100_gr_trap_sm(gr, gpc, tpc, 0); in gv100_gr_trap_mp()
59 nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000); in gv100_gr_init_4188a4()
67 for (sm = 0; sm < 0x100; sm += 0x80) { in gv100_gr_init_shader_exceptions()
68 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64); in gv100_gr_init_shader_exceptions()
69 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001); in gv100_gr_init_shader_exceptions()
[all …]
/Linux-v5.15/include/linux/mfd/mt6358/
Dregisters.h10 #define MT6358_SWCID 0xa
11 #define MT6358_TOPSTATUS 0x28
12 #define MT6358_TOP_RST_MISC 0x14c
13 #define MT6358_MISC_TOP_INT_CON0 0x188
14 #define MT6358_MISC_TOP_INT_STATUS0 0x194
15 #define MT6358_TOP_INT_STATUS0 0x19e
16 #define MT6358_SCK_TOP_INT_CON0 0x52e
17 #define MT6358_SCK_TOP_INT_STATUS0 0x53a
18 #define MT6358_EOSC_CALI_CON0 0x540
19 #define MT6358_EOSC_CALI_CON1 0x542
[all …]
/Linux-v5.15/drivers/nvmem/
Dvf610-ocotp.c23 #define OCOTP_CTRL_REG 0x00
24 #define OCOTP_CTRL_SET 0x04
25 #define OCOTP_CTRL_CLR 0x08
26 #define OCOTP_TIMING 0x10
27 #define OCOTP_DATA 0x20
28 #define OCOTP_READ_CTRL_REG 0x30
29 #define OCOTP_READ_FUSE_DATA 0x40
33 #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77
35 #define OCOTP_CTRL_ADDR 0
36 #define OCOTP_CTRL_ADDR_MASK GENMASK(6, 0)
[all …]
/Linux-v5.15/drivers/iio/adc/
Dep93xx_adc.c39 #define EP93XX_ADC_RESULT 0x08
41 #define EP93XX_ADC_SWITCH 0x18
42 #define EP93XX_ADC_SW_LOCK 0x20
63 * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
68 EP93XX_ADC_CH(0, "YM", 0x608),
69 EP93XX_ADC_CH(1, "SXP", 0x680),
70 EP93XX_ADC_CH(2, "SXM", 0x640),
71 EP93XX_ADC_CH(3, "SYP", 0x620),
72 EP93XX_ADC_CH(4, "SYM", 0x610),
73 EP93XX_ADC_CH(5, "XP", 0x601),
[all …]
/Linux-v5.15/drivers/net/ethernet/cavium/thunder/
Dthunder_bgx.h10 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
11 #define PCI_DEVICE_ID_THUNDER_RGX 0xA054
14 #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126
15 #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226
16 #define PCI_SUBSYS_DEVID_81XX_RGX 0xA254
17 #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326
27 #define DEFAULT_PAUSE_TIME 0xFFFF
29 #define BGX_ID_MASK 0x3
30 #define LMAC_ID_MASK 0x3
35 #define BGX_CMRX_CFG 0x00
[all …]
/Linux-v5.15/drivers/net/dsa/sja1105/
Dsja1105_spi.c21 memset(buf, 0, size); in sja1105_spi_message_pack()
38 u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0}; in sja1105_xfer()
40 struct spi_transfer xfers[2] = {0}; in sja1105_xfer()
45 int rc, i = 0; in sja1105_xfer()
53 hdr_xfer = &xfers[0]; in sja1105_xfer()
56 for (i = 0; i < num_chunks; i++) { in sja1105_xfer()
67 msg.read_count = 0; in sja1105_xfer()
106 if (rc < 0) { in sja1105_xfer()
112 return 0; in sja1105_xfer()
139 sja1105_pack(packed_buf, value, 63, 0, 8); in sja1105_xfer_u64()
[all …]
/Linux-v5.15/drivers/net/dsa/
Dqca8k.h18 #define PHY_ID_QCA8327 0x004dd034
19 #define QCA8K_ID_QCA8327 0x12
20 #define PHY_ID_QCA8337 0x004dd036
21 #define QCA8K_ID_QCA8337 0x13
27 #define QCA8K_CPU_PORT 0
32 #define QCA8K_REG_MASK_CTRL 0x000
33 #define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
34 #define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
37 #define QCA8K_REG_PORT0_PAD_CTRL 0x004
38 #define QCA8K_REG_PORT5_PAD_CTRL 0x008
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
37 reg = <0x00000000 0x04000000>; // 64MB
44 ranges = <0 0xf0000000 0x0000c000>;
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
38 reg = <0x00000000 0x04000000>; // 64MB
45 ranges = <0 0xf0000000 0x0000c000>;
[all …]
/Linux-v5.15/drivers/mtd/nand/raw/
Ddenali.h17 #define DEVICE_RESET 0x0
20 #define TRANSFER_SPARE_REG 0x10
21 #define TRANSFER_SPARE_REG__FLAG BIT(0)
23 #define LOAD_WAIT_CNT 0x20
24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
26 #define PROGRAM_WAIT_CNT 0x30
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
29 #define ERASE_WAIT_CNT 0x40
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
32 #define INT_MON_CYCCNT 0x50
[all …]
/Linux-v5.15/include/linux/mfd/mt6359/
Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_MISC_TOP_INT_CON0 0x188
12 #define MT6359_MISC_TOP_INT_STATUS0 0x194
13 #define MT6359_TOP_INT_STATUS0 0x19e
14 #define MT6359_SCK_TOP_INT_CON0 0x528
15 #define MT6359_SCK_TOP_INT_STATUS0 0x534
16 #define MT6359_EOSC_CALI_CON0 0x53a
17 #define MT6359_EOSC_CALI_CON1 0x53c
18 #define MT6359_RTC_MIX_CON0 0x53e
19 #define MT6359_RTC_MIX_CON1 0x540
[all …]
/Linux-v5.15/drivers/gpu/drm/exynos/
Dregs-decon7.h11 #define VIDCON0 0x00
16 #define VIDCON0_ENVID_F (1 << 0)
19 #define VIDOUTCON0 0x4
21 #define VIDOUTCON0_DUAL_MASK (0x3 << 24)
22 #define VIDOUTCON0_DUAL_ON (0x3 << 24)
23 #define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)
24 #define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
25 #define VIDOUTCON0_DUAL_OFF (0x0 << 24)
27 #define VIDOUTCON0_IF_MASK (0x1 << 23)
28 #define VIDOUTCON0_RGBIF (0x0 << 23)
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_lrc.c25 #define POSTED BIT(0) in set_offsets()
26 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
28 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
29 (((x) >> 2) & 0x7f) in set_offsets()
30 #define END 0 in set_offsets()
43 count = *data & 0x3f; in set_offsets()
56 u32 offset = 0; in set_offsets()
65 regs[0] = base + (offset << 2); in set_offsets()
74 *regs |= BIT(0); in set_offsets()
80 LRI(11, 0),
[all …]
/Linux-v5.15/drivers/gpu/drm/radeon/
Dsumod.h30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
[all …]
/Linux-v5.15/include/linux/
Dqcom-geni-se.h75 #define GENI_FORCE_DEFAULT_REG 0x20
76 #define SE_GENI_STATUS 0x40
77 #define GENI_SER_M_CLK_CFG 0x48
78 #define GENI_SER_S_CLK_CFG 0x4c
79 #define GENI_IF_DISABLE_RO 0x64
80 #define GENI_FW_REVISION_RO 0x68
81 #define SE_GENI_CLK_SEL 0x7c
82 #define SE_GENI_DMA_MODE_EN 0x258
83 #define SE_GENI_M_CMD0 0x600
84 #define SE_GENI_M_CMD_CTRL_REG 0x604
[all …]

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