Lines Matching +full:0 +full:x610
18 #define PHY_ID_QCA8327 0x004dd034
19 #define QCA8K_ID_QCA8327 0x12
20 #define PHY_ID_QCA8337 0x004dd036
21 #define QCA8K_ID_QCA8337 0x13
27 #define QCA8K_CPU_PORT 0
32 #define QCA8K_REG_MASK_CTRL 0x000
33 #define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
34 #define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
37 #define QCA8K_REG_PORT0_PAD_CTRL 0x004
38 #define QCA8K_REG_PORT5_PAD_CTRL 0x008
39 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
47 #define QCA8K_REG_PWS 0x010
49 #define QCA8K_REG_MODULE_EN 0x030
50 #define QCA8K_MODULE_EN_MIB BIT(0)
51 #define QCA8K_REG_MIB 0x034
55 #define QCA8K_MDIO_MASTER_CTRL 0x3c
59 #define QCA8K_MDIO_MASTER_WRITE 0
64 #define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
67 #define QCA8K_GOL_MAC_ADDR0 0x60
68 #define QCA8K_GOL_MAC_ADDR1 0x64
69 #define QCA8K_MAX_FRAME_SIZE 0x78
70 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
71 #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
72 #define QCA8K_PORT_STATUS_SPEED_10 0
73 #define QCA8K_PORT_STATUS_SPEED_100 0x1
74 #define QCA8K_PORT_STATUS_SPEED_1000 0x2
84 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
87 #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
88 #define QCA8K_PORT_HDR_CTRL_TX_S 0
91 #define QCA8K_PORT_HDR_CTRL_NONE 0
92 #define QCA8K_REG_SGMII_CTRL 0x0e0
99 #define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
104 #define QCA8K_REG_EEE_CTRL 0x100
108 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
111 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
112 #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
113 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
116 #define QCA8K_REG_ATU_DATA0 0x600
120 #define QCA8K_REG_ATU_DATA1 0x604
121 #define QCA8K_ATU_PORT_M 0x7f
124 #define QCA8K_REG_ATU_DATA2 0x608
125 #define QCA8K_ATU_VID_M 0xfff
127 #define QCA8K_ATU_STATUS_M 0xf
128 #define QCA8K_ATU_STATUS_STATIC 0xf
129 #define QCA8K_REG_ATU_FUNC 0x60c
134 #define QCA8K_ATU_FUNC_PORT_M 0xf
136 #define QCA8K_REG_VTU_FUNC0 0x610
141 #define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
145 #define QCA8K_REG_VTU_FUNC1 0x614
149 #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
151 #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
155 #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
156 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
157 #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
159 #define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
164 #define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
172 #define QCA8K_REG_GLOBAL_FC_THRESH 0x800
175 #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
176 #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
178 #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
179 #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
180 #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
194 #define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
195 #define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
196 #define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
203 #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
206 #define QCA8K_HROUTER_CONTROL 0xe00
210 #define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
211 #define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
212 #define QCA8K_HNAT_CONTROL 0xe38
215 #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
218 #define MII_ATH_MMD_ADDR 0x0d
219 #define MII_ATH_MMD_DATA 0x0e
222 QCA8K_PORT_SPEED_10M = 0,