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/Linux-v5.4/arch/arm64/boot/dts/freescale/
Dqoriq-bman-portals.dtsi14 bman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
26 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
32 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
38 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
44 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
50 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
56 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
62 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
68 reg = <0x80000 0x4000>, <0x4080000 0x4000>;
[all …]
Dqoriq-qman-portals.dtsi14 qportal0: qman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
22 cell-index = <0>;
27 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
34 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
41 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
48 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
55 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
62 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
69 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
[all …]
/Linux-v5.4/arch/powerpc/boot/dts/fsl/
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
Dqoriq-qman1-portals.dtsi40 qportal0: qman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <104 2 0 0>;
44 cell-index = <0x0>;
48 reg = <0x4000 0x4000>, <0x101000 0x1000>;
49 interrupts = <106 2 0 0>;
54 reg = <0x8000 0x4000>, <0x102000 0x1000>;
55 interrupts = <108 2 0 0>;
60 reg = <0xc000 0x4000>, <0x103000 0x1000>;
61 interrupts = <110 2 0 0>;
[all …]
Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dimx25.dtsi47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
60 reg = <0x68000000 0x8000000>;
66 #clock-cells = <0>;
82 reg = <0x43f00000 0x100000>;
87 reg = <0x43f00000 0x4000>;
92 #size-cells = <0>;
94 reg = <0x43f80000 0x4000>;
103 #size-cells = <0>;
[all …]
Dimx50.dtsi48 #size-cells = <0>;
49 cpu@0 {
52 reg = <0x0>;
60 reg = <0x0fffc000 0x4000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
79 clock-frequency = <0>;
84 #clock-cells = <0>;
89 usbphy0: usbphy-0 {
[all …]
Dimx31.dtsi35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0>;
48 reg = <0x68000000 0x100000>;
60 reg = <0x1fffc000 0x4000>;
63 ranges = <0 0x1fffc000 0x4000>;
70 reg = <0x43f00000 0x100000>;
75 reg = <0x43f80000 0x4000>;
79 #size-cells = <0>;
85 reg = <0x43f84000 0x4000>;
[all …]
Dimx6sx.dtsi58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
95 #clock-cells = <0>;
102 #clock-cells = <0>;
109 #clock-cells = <0>;
110 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
123 #clock-cells = <0>;
[all …]
Dimx6ul.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
129 #clock-cells = <0>;
130 clock-frequency = <0>;
159 reg = <0x00900000 0x20000>;
[all …]
Dimx51.dtsi46 reg = <0xe0000000 0x4000>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 #size-cells = <0>;
78 cpu: cpu@0 {
81 reg = <0>;
[all …]
Dimx6qdl.dtsi55 #clock-cells = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
75 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
79 #thermal-sensor-cells = <0>;
84 #size-cells = <0>;
89 lvds-channel@0 {
91 #size-cells = <0>;
92 reg = <0>;
[all …]
Dimx53.dtsi51 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0>;
84 reg = <0x0fffc000 0x4000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
102 #clock-cells = <0>;
103 clock-frequency = <0>;
108 #clock-cells = <0>;
119 usbphy0: usbphy-0 {
[all …]
Dimx6sl.dtsi48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0x0>;
83 #clock-cells = <0>;
89 #clock-cells = <0>;
96 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
106 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
111 #phy-cells = <0>;
123 reg = <0x00900000 0x20000>;
131 reg = <0x00a01000 0x1000>,
[all …]
Dimx6sll.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0>;
80 #clock-cells = <0>;
87 #clock-cells = <0>;
94 #clock-cells = <0>;
95 clock-frequency = <0>;
101 #clock-cells = <0>;
102 clock-frequency = <0>;
125 reg = <0x00900000 0x20000>;
[all …]
Dimx35.dtsi39 #size-cells = <0>;
41 cpu@0 {
44 reg = <0>;
52 reg = <0x68000000 0x10000000>;
64 reg = <0x30000000 0x1000>;
73 reg = <0x43f00000 0x100000>;
78 #size-cells = <0>;
80 reg = <0x43f80000 0x4000>;
89 #size-cells = <0>;
91 reg = <0x43f84000 0x4000>;
[all …]
/Linux-v5.4/drivers/net/ethernet/amd/
Dam79c961a.h9 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
15 #define NET_DEBUG 0
18 #define NET_UID 0
19 #define NET_RDP 0x10
20 #define NET_RAP 0x12
21 #define NET_RESET 0x14
22 #define NET_IDP 0x16
27 #define CSR0 0
28 #define CSR0_INIT 0x0001
29 #define CSR0_STRT 0x0002
[all …]
/Linux-v5.4/include/linux/mfd/wm8350/
Daudio.h13 #define WM8350_CLOCK_CONTROL_1 0x28
14 #define WM8350_CLOCK_CONTROL_2 0x29
15 #define WM8350_FLL_CONTROL_1 0x2A
16 #define WM8350_FLL_CONTROL_2 0x2B
17 #define WM8350_FLL_CONTROL_3 0x2C
18 #define WM8350_FLL_CONTROL_4 0x2D
19 #define WM8350_DAC_CONTROL 0x30
20 #define WM8350_DAC_DIGITAL_VOLUME_L 0x32
21 #define WM8350_DAC_DIGITAL_VOLUME_R 0x33
22 #define WM8350_DAC_LR_RATE 0x35
[all …]
/Linux-v5.4/drivers/net/wireless/broadcom/b43/
Dphy_ac.h7 #define B43_PHY_AC_BBCFG 0x001
8 #define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */
9 #define B43_PHY_AC_BANDCTL 0x003 /* Band control */
10 #define B43_PHY_AC_BANDCTL_5GHZ 0x0001
11 #define B43_PHY_AC_TABLE_ID 0x00d
12 #define B43_PHY_AC_TABLE_OFFSET 0x00e
13 #define B43_PHY_AC_TABLE_DATA1 0x00f
14 #define B43_PHY_AC_TABLE_DATA2 0x010
15 #define B43_PHY_AC_TABLE_DATA3 0x011
16 #define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */
[all …]
/Linux-v5.4/drivers/net/dsa/mv88e6xxx/
Dglobal2.h16 /* Offset 0x00: Interrupt Source Register */
17 #define MV88E6XXX_G2_INT_SRC 0x00
18 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
22 #define MV88E6352_G2_INT_SRC_SERDES 0x0800
23 #define MV88E6352_G2_INT_SRC_PHY 0x001f
24 #define MV88E6390_G2_INT_SRC_PHY 0x07fe
28 /* Offset 0x01: Interrupt Mask Register */
[all …]

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