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/Linux-v5.15/drivers/clk/renesas/
Dr8a774a1-cpg-mssr.c82 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
104 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
105 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
106 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
112 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
113 DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
114 DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
115 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
128 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
[all …]
Dr8a774e1-cpg-mssr.c82 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
113 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
115 DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
116 DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
[all …]
Dr8a7796-cpg-mssr.c87 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
109 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
110 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
111 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
119 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
120 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
121 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
122 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
[all …]
Dr8a7795-cpg-mssr.c85 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
107 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
108 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
109 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
110 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
117 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
118 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
119 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
120 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
[all …]
Dr8a774b1-cpg-mssr.c100 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
101 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
102 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
103 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
109 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
110 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
111 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
112 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
256 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
Dr8a77965-cpg-mssr.c104 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
105 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
114 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
115 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
116 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
117 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
284 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
/Linux-v5.15/drivers/media/usb/gspca/
Dkonica.c29 #define WHITEBAL_REG 0x01
30 #define BRIGHTNESS_REG 0x02
31 #define SHARPNESS_REG 0x03
32 #define CONTRAST_REG 0x04
33 #define SATURATION_REG 0x05
44 0x00 -> 176x144, cropped
45 0x01 -> 176x144, cropped
46 0x02 -> 176x144, cropped
47 0x03 -> 176x144, cropped
48 0x04 -> 176x144, binned
[all …]
Dxirlink_cit.c29 module_param(ibm_netcam_pro, int, 0);
44 #define CIT_MODEL0 0 /* bcd version 0.01 cams ie the xvp-500 */
125 {0, 0x0000, 0x010c},
126 {0, 0x0006, 0x012c},
127 {0, 0x0078, 0x012d},
128 {0, 0x0046, 0x012f},
129 {0, 0xd141, 0x0124},
130 {0, 0x0000, 0x0127},
131 {0, 0xfea8, 0x0124},
132 {1, 0x0000, 0x0116},
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/Linux-v5.15/drivers/hwtracing/coresight/
Dcoresight-cti.h22 * 0x000 - 0x144: CTI programming and status
23 * 0xEDC - 0xEF8: CTI integration test.
24 * 0xF00 - 0xFFC: Coresight management registers.
27 #define CTICONTROL 0x000
28 #define CTIINTACK 0x010
29 #define CTIAPPSET 0x014
30 #define CTIAPPCLEAR 0x018
31 #define CTIAPPPULSE 0x01C
32 #define CTIINEN(n) (0x020 + (4 * n))
33 #define CTIOUTEN(n) (0x0A0 + (4 * n))
[all …]
/Linux-v5.15/arch/arm/mach-davinci/
Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/Linux-v5.15/drivers/scsi/ufs/
Dufs-mediatek.h15 #define REG_UFS_REFCLK_CTRL 0x144
16 #define REG_UFS_EXTREG 0x2100
17 #define REG_UFS_MPHYCTRL 0x2200
18 #define REG_UFS_REJECT_MON 0x22AC
19 #define REG_UFS_DEBUG_SEL 0x22C0
20 #define REG_UFS_PROBE 0x22C8
27 #define REFCLK_RELEASE 0x0
28 #define REFCLK_REQUEST BIT(0)
36 #define VS_DEBUGCLOCKENABLE 0xD0A1
37 #define VS_SAVEPOWERCONTROL 0xD0A6
[all …]
/Linux-v5.15/drivers/mmc/host/
Dsdhci-esdhc.h27 #define ESDHC_HOST_CONTROL_LE 0x20
34 #define ESDHC_PRSSTAT 0x24
35 #define ESDHC_CLOCK_GATE_OFF 0x00000080
36 #define ESDHC_CLOCK_STABLE 0x00000008
39 #define ESDHC_PROCTL 0x28
40 #define ESDHC_VOLT_SEL 0x00000400
41 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
42 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
43 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
44 #define ESDHC_HOST_CONTROL_RES 0x01
[all …]
/Linux-v5.15/arch/arm/mach-mmp/
Dregs-icu.h11 #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
14 #define ICU2_VIRT_BASE (AXI_VIRT_BASE + 0x84000)
18 #define ICU_INT_CONF_MASK (0xf)
25 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26 #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27 #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28 #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29 #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
41 #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
42 #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
[all …]
/Linux-v5.15/drivers/media/usb/gspca/stv06xx/
Dstv06xx.h25 #define STV_ISOC_ENDPOINT_ADDR 0x81
27 #define STV_R 0x0509
29 #define STV_REG23 0x0423
32 #define STV_I2C_PARTNER 0x1420
33 #define STV_I2C_VAL_REG_VAL_PAIRS_MIN1 0x1421
34 #define STV_I2C_READ_WRITE_TOGGLE 0x1422
35 #define STV_I2C_FLUSH 0x1423
36 #define STV_I2C_SUCC_READ_REG_VALS 0x1424
38 #define STV_ISO_ENABLE 0x1440
39 #define STV_SCAN_RATE 0x1443
[all …]
/Linux-v5.15/drivers/usb/gadget/udc/
Dfotg210.h14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]
/Linux-v5.15/drivers/pinctrl/
Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
[all …]
/Linux-v5.15/drivers/net/wireless/marvell/mwifiex/
Dcfp.c40 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
42 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
43 0xb0, 0x48, 0x60, 0x6c, 0 };
45 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
46 0x0c, 0x12, 0x18, 0x24,
47 0x30, 0x48, 0x60, 0x6c, 0 };
49 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
50 0xb0, 0x48, 0x60, 0x6c, 0 };
51 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
52 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
/Linux-v5.15/drivers/hwmon/
Dintel-m10-bmc-hwmon.c39 { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Temperature" },
40 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Die Temperature" },
41 { 0x11c, 0x124, 0x120, 0x0, 0x0, 500, "QSFP0 Temperature" },
42 { 0x12c, 0x134, 0x130, 0x0, 0x0, 500, "QSFP1 Temperature" },
43 { 0x168, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A Temperature" },
44 { 0x16c, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A SerDes Temperature" },
45 { 0x170, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B Temperature" },
46 { 0x174, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B SerDes Temperature" },
50 { 0x128, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },
51 { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/Linux-v5.15/drivers/crypto/qat/qat_common/
Dicp_qat_hal.h8 MISC_CONTROL = 0xA04,
9 ICP_RESET = 0xA0c,
10 ICP_GLOBAL_CLK_ENABLE = 0xA50
14 MISC_CONTROL_C4XXX = 0xAA0,
15 ICP_RESET_CPP0 = 0x938,
16 ICP_RESET_CPP1 = 0x93c,
17 ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964,
18 ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968
22 USTORE_ADDRESS = 0x000,
23 USTORE_DATA_LOWER = 0x004,
[all …]
/Linux-v5.15/drivers/clk/meson/
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/Linux-v5.15/include/linux/
Dtifm.h19 FM_SET_INTERRUPT_ENABLE = 0x008,
20 FM_CLEAR_INTERRUPT_ENABLE = 0x00c,
21 FM_INTERRUPT_STATUS = 0x014
26 SOCK_CONTROL = 0x004,
27 SOCK_PRESENT_STATE = 0x008,
28 SOCK_DMA_ADDRESS = 0x00c,
29 SOCK_DMA_CONTROL = 0x010,
30 SOCK_DMA_FIFO_INT_ENABLE_SET = 0x014,
31 SOCK_DMA_FIFO_INT_ENABLE_CLEAR = 0x018,
32 SOCK_DMA_FIFO_STATUS = 0x020,
[all …]

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