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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mm-venice-gw7902.dts30 reg = <0x0 0x40000000 0 0x80000000>;
35 #clock-cells = <0>;
53 interrupts = <0>;
88 pinctrl-0 = <&pinctrl_gpio_leds>;
90 led-0 {
134 pinctrl-0 = <&pinctrl_pps>;
150 pinctrl-0 = <&pinctrl_reg_usb1>;
161 pinctrl-0 = <&pinctrl_reg_wl>;
209 pinctrl-0 = <&pinctrl_spi1>;
213 can@0 {
[all …]
Dimx8mm-nitrogen-r2.dts30 pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
57 pinctrl-0 = <&pinctrl_sound_wm8960>;
83 pinctrl-0 = <&pinctrl_ecspi2>;
90 pinctrl-0 = <&pinctrl_fec1>;
98 #size-cells = <0>;
110 pinctrl-0 = <&pinctrl_flexspi>;
117 pinctrl-0 = <&pinctrl_i2c1>;
122 reg = <0x8>;
214 pinctrl-0 = <&pinctrl_i2c3>;
219 reg = <0x70>;
[all …]
Dimx8mm-kontron-n801x-s.dts21 #clock-cells = <0>;
29 pinctrl-0 = <&pinctrl_gpio_led>;
65 pwms = <&pwm2 0 5000 0>;
72 pinctrl-0 = <&pinctrl_usb_eth2>;
88 pinctrl-0 = <&pinctrl_ecspi2>;
92 can0: can@0 {
94 reg = <0>;
96 pinctrl-0 = <&pinctrl_can>;
108 pinctrl-0 = <&pinctrl_ecspi3>;
115 pinctrl-0 = <&pinctrl_enet>;
[all …]
Dimx8mm-venice-gw7901.dts34 reg = <0x0 0x40000000 0 0x80000000>;
50 interrupts = <0>;
85 led-0 {
89 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
191 pinctrl-0 = <&pinctrl_reg_ioexp>;
204 pinctrl-0 = <&pinctrl_reg_isouart>;
216 pinctrl-0 = <&pinctrl_reg_usb2>;
227 pinctrl-0 = <&pinctrl_reg_wl>;
260 pinctrl-0 = <&pinctrl_spi1>;
264 flash@0 {
[all …]
Dimx8mm-venice-gw73xx.dtsi18 pinctrl-0 = <&pinctrl_gpio_leds>;
20 led-0 {
39 pinctrl-0 = <&pinctrl_pps>;
62 pinctrl-0 = <&pinctrl_reg_usb1_en>;
73 pinctrl-0 = <&pinctrl_reg_usb2_en>;
84 pinctrl-0 = <&pinctrl_reg_wl>;
98 pinctrl-0 = <&pinctrl_spi2>;
106 pinctrl-0 = <&pinctrl_i2c2>;
111 pinctrl-0 = <&pinctrl_accel>;
113 reg = <0x19>;
[all …]
Dimx8mm-venice-gw72xx.dtsi18 pinctrl-0 = <&pinctrl_gpio_leds>;
20 led-0 {
39 pinctrl-0 = <&pinctrl_pps>;
54 pinctrl-0 = <&pinctrl_reg_usb1_en>;
65 pinctrl-0 = <&pinctrl_reg_usb2_en>;
78 pinctrl-0 = <&pinctrl_spi2>;
86 pinctrl-0 = <&pinctrl_i2c2>;
91 pinctrl-0 = <&pinctrl_accel>;
93 reg = <0x19>;
105 pinctrl-0 = <&pinctrl_i2c3>;
[all …]
Dimx8mm-venice-gw71xx.dtsi18 pinctrl-0 = <&pinctrl_gpio_leds>;
20 led-0 {
39 pinctrl-0 = <&pinctrl_pps>;
46 pinctrl-0 = <&pinctrl_reg_usb1_en>;
59 pinctrl-0 = <&pinctrl_spi2>;
67 pinctrl-0 = <&pinctrl_i2c2>;
72 pinctrl-0 = <&pinctrl_accel>;
74 reg = <0x19>;
86 pinctrl-0 = <&pinctrl_i2c3>;
93 pinctrl-0 = <&pinctrl_uart1>;
[all …]
Dimx8mn-venice-gw7902.dts29 reg = <0x0 0x40000000 0 0x80000000>;
34 #clock-cells = <0>;
52 interrupts = <0>;
87 pinctrl-0 = <&pinctrl_gpio_leds>;
89 led-0 {
133 pinctrl-0 = <&pinctrl_pps>;
149 pinctrl-0 = <&pinctrl_reg_usb1>;
160 pinctrl-0 = <&pinctrl_reg_wl>;
208 pinctrl-0 = <&pinctrl_spi1>;
212 can@0 {
[all …]
Dimx8mn-var-som-symphony.dts18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
53 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
66 pinctrl-0 = <&pinctrl_i2c2>;
71 reg = <0x20>;
74 pinctrl-0 = <&pinctrl_pca9534>;
105 reg = <0x3d>;
109 pinctrl-0 = <&pinctrl_ptn5150>;
118 reg = <0x38>;
120 pinctrl-0 = <&pinctrl_captouch>;
132 reg = <0x68>;
[all …]
Dimx8mm-var-som-symphony.dts17 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28 pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
63 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
76 pinctrl-0 = <&pinctrl_i2c2>;
81 reg = <0x20>;
84 pinctrl-0 = <&pinctrl_pca9534>;
115 reg = <0x3d>;
119 pinctrl-0 = <&pinctrl_ptn5150>;
128 reg = <0x38>;
130 pinctrl-0 = <&pinctrl_captouch>;
[all …]
Dimx8mn-var-som.dtsi20 reg = <0x0 0x40000000 0 0x40000000>;
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
53 pinctrl-0 = <&pinctrl_ecspi1>;
55 <&gpio1 0 GPIO_ACTIVE_LOW>;
61 touchscreen@0 {
62 reg = <0>;
65 pinctrl-0 = <&pinctrl_restouch>;
89 pinctrl-0 = <&pinctrl_fec1>;
99 #size-cells = <0>;
113 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-var-som.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
25 pinctrl-0 = <&pinctrl_reg_eth_phy>;
72 pinctrl-0 = <&pinctrl_ecspi1>;
74 <&gpio1 0 GPIO_ACTIVE_LOW>;
80 touchscreen@0 {
81 reg = <0>;
84 pinctrl-0 = <&pinctrl_restouch>;
108 pinctrl-0 = <&pinctrl_fec1>;
117 #size-cells = <0>;
132 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-icore-mx8mm-edimm2.2.dts29 pinctrl-0 = <&pinctrl_i2c2>;
36 pinctrl-0 = <&pinctrl_i2c4>;
43 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
44 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
50 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
51 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
57 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
58 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
64 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
70 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
[all …]
Dimx8mm-icore-mx8mm-ctouch2.dts29 pinctrl-0 = <&pinctrl_i2c2>;
36 pinctrl-0 = <&pinctrl_i2c4>;
43 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
44 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
50 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
51 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
57 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
58 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
64 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
70 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
[all …]
Dimx8mn-beacon-som.dtsi16 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
25 reg = <0x0 0x40000000 0 0x80000000>;
74 pinctrl-0 = <&pinctrl_fec1>;
84 #size-cells = <0>;
86 ethphy0: ethernet-phy@0 {
88 reg = <0>;
95 pinctrl-0 = <&pinctrl_flexspi>;
98 flash@0 {
99 reg = <0>;
112 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-beacon-som.dtsi15 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
24 reg = <0x0 0x40000000 0 0x80000000>;
66 pinctrl-0 = <&pinctrl_fec1>;
74 #size-cells = <0>;
76 ethphy0: ethernet-phy@0 {
78 reg = <0>;
85 pinctrl-0 = <&pinctrl_flexspi>;
88 flash@0 {
89 reg = <0>;
102 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-beacon-baseboard.dtsi30 pinctrl-0 = <&pinctrl_led3>;
72 pinctrl-0 = <&pinctrl_espi2>;
76 eeprom@0 {
78 reg = <0>;
91 pinctrl-0 = <&pinctrl_i2c2>;
98 pinctrl-0 = <&pinctrl_i2c4>;
103 reg = <0x1a>;
114 0x0000 /* 0:Default */
115 0x0000 /* 1:Default */
116 0x0000 /* 2:FN_DMICCLK */
[all …]
/Linux-v5.15/drivers/media/usb/go7007/
Ds2250-board.c26 #define TLV320_ADDRESS 0x34
27 #define VPX322_ADDR_ANALOGCONTROL1 0x02
28 #define VPX322_ADDR_BRIGHTNESS0 0x0127
29 #define VPX322_ADDR_BRIGHTNESS1 0x0131
30 #define VPX322_ADDR_CONTRAST0 0x0128
31 #define VPX322_ADDR_CONTRAST1 0x0132
32 #define VPX322_ADDR_HUE 0x00dc
33 #define VPX322_ADDR_SAT 0x0030
50 0x1e, 0x00,
51 0x00, 0x17,
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/amlogic/
Damlogic,meson-gx-ao-secure.yaml52 reg = <0x140 0x140>;
/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8mm-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
Dfsl,imx8mn-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
/Linux-v5.15/arch/mips/pci/
Dpci-vr41xx.h12 #define PCIU_BASE 0x0f000c00UL
13 #define PCIU_SIZE 0x200UL
15 #define PCIMMAW1REG 0x00
16 #define PCIMMAW2REG 0x04
17 #define PCITAW1REG 0x08
18 #define PCITAW2REG 0x0c
19 #define PCIMIOAWREG 0x10
20 #define IBA(addr) ((addr) & 0xff000000U)
21 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
22 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
/Linux-v5.15/drivers/mmc/host/
Dsdhci-of-sparx5.c22 #define CPU_REGS_GENERAL_CTRL (0x22 * 4)
27 #define CPU_REGS_PROC_CTRL (0x2C * 4)
33 #define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
34 #define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
35 #define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
37 #define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
80 pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value); in sparx5_set_cacheable()
109 pr_debug("%s: Set EMMC_CTRL: 0x%08x\n", in sdhci_sparx5_set_emmc()
152 .quirks = 0,
198 (value > 0 && value <= MSHC_DLY_CC_MAX)) in sdhci_sparx5_probe()
[all …]
/Linux-v5.15/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/Linux-v5.15/drivers/soc/rockchip/
Dgrf.c28 #define RK3036_GRF_SOC_CON0 0x140
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
43 #define RK3128_GRF_SOC_CON0 0x140
46 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
54 #define RK3228_GRF_SOC_CON6 0x418
57 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
65 #define RK3288_GRF_SOC_CON0 0x244
66 #define RK3288_GRF_SOC_CON2 0x24c
69 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
70 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
[all …]

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