Lines Matching +full:0 +full:x140
22 #define CPU_REGS_GENERAL_CTRL (0x22 * 4)
27 #define CPU_REGS_PROC_CTRL (0x2C * 4)
33 #define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
34 #define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
35 #define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
37 #define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
80 pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value); in sparx5_set_cacheable()
109 pr_debug("%s: Set EMMC_CTRL: 0x%08x\n", in sdhci_sparx5_set_emmc()
152 .quirks = 0,
198 (value > 0 && value <= MSHC_DLY_CC_MAX)) in sdhci_sparx5_probe()
214 if (sdhci_sparx5->delay_clock >= 0) in sdhci_sparx5_probe()
235 pr_debug("%s: SDHC version: 0x%08x\n", in sdhci_sparx5_probe()
237 pr_debug("%s: SDHC type: 0x%08x\n", in sdhci_sparx5_probe()