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/Linux-v5.15/Documentation/devicetree/bindings/thermal/
Dthermal-sensor.yaml35 0 on sensor nodes with only a single sensor and at least 1 on nodes
37 enum: [0, 1]
57 reg = <0 0x0c263000 0 0x1ff>, /* TM */
58 <0 0x0c222000 0 0x1ff>; /* SROT */
68 reg = <0 0x0c265000 0 0x1ff>, /* TM */
69 <0 0x0c223000 0 0x1ff>; /* SROT */
Dthermal-zones.yaml65 checking this thermal zone. Setting this to 0 disables the polling
74 this to 0 disables the polling timers setup by the thermal
115 "^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$":
202 minimum: 0
237 reg = <0 0x0c263000 0 0x1ff>, /* TM */
238 <0 0x0c222000 0 0x1ff>; /* SROT */
248 reg = <0 0x0c265000 0 0x1ff>, /* TM */
249 <0 0x0c223000 0 0x1ff>; /* SROT */
/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsm8350.dtsi28 #clock-cells = <0>;
36 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x100>;
67 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x200>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7280.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
53 reg = <0x0 0x80800000 0x0 0x60000>;
58 reg = <0x0 0x80860000 0x0 0x20000>;
64 reg = <0x0 0x80900000 0x0 0x200000>;
70 reg = <0x0 0x80b00000 0x0 0x100000>;
74 reg = <0 0x8b700000 0 0x10000>;
81 #size-cells = <0>;
83 CPU0: cpu@0 {
86 reg = <0x0 0x0>;
[all …]
Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
74 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0x0 0x200>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi62 #clock-cells = <0>;
68 #clock-cells = <0>;
78 reg = <0x0 0x80000000 0x0 0x600000>;
83 reg = <0x0 0x80600000 0x0 0x200000>;
88 reg = <0x0 0x80800000 0x0 0x20000>;
93 reg = <0x0 0x80820000 0x0 0x20000>;
99 reg = <0x0 0x808ff000 0x0 0x1000>;
104 reg = <0x0 0x80900000 0x0 0x200000>;
109 reg = <0x0 0x80b00000 0x0 0x3900000>;
114 reg = <0 0x8b700000 0 0x10000>;
[all …]
Dsm8250.dtsi78 #clock-cells = <0>;
86 #clock-cells = <0>;
92 #size-cells = <0>;
94 CPU0: cpu@0 {
97 reg = <0x0 0x0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
116 reg = <0x0 0x100>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
132 reg = <0x0 0x200>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]