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/Linux-v5.10/arch/x86/platform/ce4100/
Dfalconfalls.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
27 #address-cells = <1>;
[all …]
/Linux-v5.10/drivers/misc/habanalabs/goya/
Dgoya_security.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
12 * goya_set_block_as_protected - set the given block as protected
20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in goya_pb_set_block()
22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
68 word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2; in goya_init_mme_protection_bits()
[all …]
/Linux-v5.10/drivers/media/dvb-frontends/
Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #define STV090x_MID 0xf100
16 #define STV090x_OFFST_MRELEASE_FIELD 0
19 #define STV090x_DACR1 0xf113
22 #define STV090x_OFFST_DACR1_VALUE_FIELD 0
25 #define STV090x_DACR2 0xf114
26 #define STV090x_OFFST_DACR2_VALUE_FIELD 0
29 #define STV090x_OUTCFG 0xf11c
39 #define STV090x_MODECFG 0xf11d
41 #define STV090x_IRQSTATUS3 0xf120
[all …]
/Linux-v5.10/arch/powerpc/boot/dts/fsl/
Dmpc8641_hpcn_36b.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2008-2009 Freescale Semiconductor Inc.
8 /include/ "mpc8641si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
18 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
22 reg = <0x0f 0xffe05000 0x0 0x1000>;
24 ranges = <0 0 0xf 0xef800000 0x00800000
25 2 0 0xf 0xffdf8000 0x00008000
26 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
Dmpc8641_hpcn.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8641si-pre.dtsi"
16 reg = <0x00000000 0x40000000>; // 1G at 0x0
20 reg = <0xffe05000 0x1000>;
22 ranges = <0 0 0xef800000 0x00800000
23 2 0 0xffdf8000 0x00008000
24 3 0 0xffdf0000 0x00008000>;
26 flash@0,0 {
27 compatible = "cfi-flash";
28 reg = <0 0 0x00800000>;
[all …]
/Linux-v5.10/drivers/gpu/drm/panel/
Dpanel-truly-nt35597.c1 // SPDX-License-Identifier: GPL-2.0
64 struct mipi_dsi_device *dsi[2];
78 { { 0xff, 0x20 }, 2 },
79 { { 0xfb, 0x01 }, 2 },
80 { { 0x00, 0x01 }, 2 },
81 { { 0x01, 0x55 }, 2 },
82 { { 0x02, 0x45 }, 2 },
83 { { 0x05, 0x40 }, 2 },
84 { { 0x06, 0x19 }, 2 },
85 { { 0x07, 0x1e }, 2 },
[all …]
/Linux-v5.10/arch/xtensa/variants/test_kc705_be/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
/Linux-v5.10/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
/Linux-v5.10/arch/arm64/crypto/
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
17 .set .Lv\b\().2d, \b
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
29 .inst 0xcec08000 | .L\rd | (.L\rn << 5)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
[all …]
/Linux-v5.10/arch/xtensa/variants/de212/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 0 /* number of coprocessors */
36 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
40 /* Save area for non-coprocessor optional and custom (TIE) state: */
45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
/Linux-v5.10/arch/xtensa/variants/csp/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
43 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
45 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
48 #define XCHAL_CP0_SA_SIZE 0
50 #define XCHAL_CP1_SA_SIZE 0
52 #define XCHAL_CP2_SA_SIZE 0
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/sandybridge/
Dpipeline.json4 "Counter": "Fixed counter 2",
5 "UMask": "0x3",
9 "CounterHTOff": "Fixed counter 2"
12 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
13 "Counter": "Fixed counter 0",
14 "UMask": "0x1",
18 "CounterHTOff": "Fixed counter 0"
23 "UMask": "0x2",
31 "UMask": "0x2",
39 "EventCode": "0x03",
[all …]
/Linux-v5.10/arch/mips/kernel/
Dmips-r2-to-r6-emul.c28 #include <asm/mips-r2-to-r6-emul.h>
59 int mipsr2_emulation = 0;
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
86 return 0; in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
95 return 0; in mipsr6_emul()
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/ivybridge/
Dpipeline.json3 "Counter": "Fixed counter 0",
4 "UMask": "0x1",
8 "CounterHTOff": "Fixed counter 0"
12 "UMask": "0x2",
21 "UMask": "0x2",
29 "Counter": "Fixed counter 2",
30 "UMask": "0x3",
34 "CounterHTOff": "Fixed counter 2"
38 "EventCode": "0x03",
39 "Counter": "0,1,2,3",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/ivytown/
Dpipeline.json3 "Counter": "Fixed counter 0",
4 "UMask": "0x1",
8 "CounterHTOff": "Fixed counter 0"
12 "UMask": "0x2",
21 "UMask": "0x2",
29 "Counter": "Fixed counter 2",
30 "UMask": "0x3",
34 "CounterHTOff": "Fixed counter 2"
38 "EventCode": "0x03",
39 "Counter": "0,1,2,3",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/jaketown/
Dpipeline.json3 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
5 "UMask": "0x1",
13 "Counter": "Fixed counter 2",
14 "UMask": "0x2",
18 "CounterHTOff": "Fixed counter 2"
23 "UMask": "0x3",
30 "EventCode": "0x88",
31 "Counter": "0,1,2,3",
32 "UMask": "0x41",
35 "BriefDescription": "Not taken macro-conditional branches.",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellx/
Dpipeline.json3 "UMask": "0x1",
5 "Counter": "Fixed counter 0",
7 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
9 "CounterHTOff": "Fixed counter 0"
12 "UMask": "0x2",
21 "UMask": "0x2",
30 "UMask": "0x3",
32 "Counter": "Fixed counter 2",
36 "CounterHTOff": "Fixed counter 2"
39 "EventCode": "0x03",
[all …]
/Linux-v5.10/drivers/misc/habanalabs/gaudi/
Dgaudi_security.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2018 HabanaLabs, Ltd.
447 * gaudi_set_block_as_protected - set the given block as protected
454 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in gaudi_pb_set_block()
456 while (pb_addr & 0xFFF) { in gaudi_pb_set_block()
457 WREG32(pb_addr, 0); in gaudi_pb_set_block()
480 WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
481 WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
482 WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
483 WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/icelake/
Dpipeline.json3 "CollectPEBSRecord": "2",
4 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
6 "UMask": "0x1",
10 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event"
13 "PEBS": "2",
15 …R) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
17 "UMask": "0x1",
24 "CollectPEBSRecord": "2",
27 "UMask": "0x2",
34 "CollectPEBSRecord": "2",
[all …]
Dcache.json3 "CollectPEBSRecord": "2",
5 "EventCode": "0x24",
6 "Counter": "0,1,2,3",
7 "UMask": "0x21",
8 "PEBScounters": "0,1,2,3",
14 "CollectPEBSRecord": "2",
15 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
16 "EventCode": "0x24",
17 "Counter": "0,1,2,3",
18 "UMask": "0x22",
[all …]
/Linux-v5.10/arch/arm/mach-omap1/
Dmux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
26 MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
27 MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
28 MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
29 MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
30 MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
31 MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
32 MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
[all …]
/Linux-v5.10/drivers/staging/fbtft/
Dfb_ssd1331.c1 // SPDX-License-Identifier: GPL-2.0
16 #define DEFAULT_GAMMA "0 2 2 2 2 2 2 2 " \
17 "2 2 2 2 2 2 2 2 " \
18 "2 2 2 2 2 2 2 2 " \
19 "2 2 2 2 2 2 2 2 " \
20 "2 2 2 2 2 2 2 2 " \
21 "2 2 2 2 2 2 2 2 " \
22 "2 2 2 2 2 2 2 2 " \
23 "2 2 2 2 2 2 2" \
27 par->fbtftops.reset(par); in init_display()
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmontplus/
Dpipeline.json3 "PEBS": "2",
5 …rupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect…
6 "Counter": "Fixed counter 0",
7 "UMask": "0x1",
18 "UMask": "0x2",
27 …nning at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect…
28 "Counter": "Fixed counter 2",
29 "UMask": "0x3",
37 "PEBS": "2",
38 "CollectPEBSRecord": "2",
[all …]
/Linux-v5.10/drivers/video/fbdev/
Datafb_utils.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * memset(_, 0, _). However their five instances add at least a kilobyte
22 * would be faster. I suspect not for simple text system - not much
30 * Unaligned read/write used requires 68020+ - think this is a problem?
52 return 0; in fb_memclear_small()
55 " lsr.l #1,%1 ; jcc 1f ; move.b %2,-(%0)\n" in fb_memclear_small()
56 "1: lsr.l #1,%1 ; jcc 1f ; move.w %2,-(%0)\n" in fb_memclear_small()
57 "1: lsr.l #1,%1 ; jcc 1f ; move.l %2,-(%0)\n" in fb_memclear_small()
58 "1: lsr.l #1,%1 ; jcc 1f ; move.l %2,-(%0) ; move.l %2,-(%0)\n" in fb_memclear_small()
61 : "d" (0), "0" ((char *)s + count), "1" (count)); in fb_memclear_small()
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellde/
Dpipeline.json3 "UMask": "0x1",
5 "Counter": "Fixed counter 0",
7 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
9 "CounterHTOff": "Fixed counter 0"
12 "UMask": "0x2",
21 "UMask": "0x2",
30 "UMask": "0x3",
32 "Counter": "Fixed counter 2",
36 "CounterHTOff": "Fixed counter 2"
39 "EventCode": "0x03",
[all …]

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