Lines Matching +full:0 +full:- +full:2
3 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
5 "UMask": "0x1",
13 "Counter": "Fixed counter 2",
14 "UMask": "0x2",
18 "CounterHTOff": "Fixed counter 2"
23 "UMask": "0x3",
30 "EventCode": "0x88",
31 "Counter": "0,1,2,3",
32 "UMask": "0x41",
35 "BriefDescription": "Not taken macro-conditional branches.",
36 "CounterHTOff": "0,1,2,3,4,5,6,7"
39 "EventCode": "0x88",
40 "Counter": "0,1,2,3",
41 "UMask": "0x81",
44 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
45 "CounterHTOff": "0,1,2,3,4,5,6,7"
48 "EventCode": "0x88",
49 "Counter": "0,1,2,3",
50 "UMask": "0x82",
53 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
54 "CounterHTOff": "0,1,2,3,4,5,6,7"
57 "EventCode": "0x88",
58 "Counter": "0,1,2,3",
59 "UMask": "0x84",
63 "CounterHTOff": "0,1,2,3,4,5,6,7"
66 "EventCode": "0x88",
67 "Counter": "0,1,2,3",
68 "UMask": "0x88",
72 "CounterHTOff": "0,1,2,3,4,5,6,7"
75 "EventCode": "0x88",
76 "Counter": "0,1,2,3",
77 "UMask": "0x90",
81 "CounterHTOff": "0,1,2,3,4,5,6,7"
84 "EventCode": "0x88",
85 "Counter": "0,1,2,3",
86 "UMask": "0xa0",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
93 "EventCode": "0x88",
94 "Counter": "0,1,2,3",
95 "UMask": "0xc1",
98 "BriefDescription": "Speculative and retired macro-conditional branches.",
99 "CounterHTOff": "0,1,2,3,4,5,6,7"
102 "EventCode": "0x88",
103 "Counter": "0,1,2,3",
104 "UMask": "0xc2",
107 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
108 "CounterHTOff": "0,1,2,3,4,5,6,7"
111 "EventCode": "0x88",
112 "Counter": "0,1,2,3",
113 "UMask": "0xc4",
117 "CounterHTOff": "0,1,2,3,4,5,6,7"
120 "EventCode": "0x88",
121 "Counter": "0,1,2,3",
122 "UMask": "0xc8",
126 "CounterHTOff": "0,1,2,3,4,5,6,7"
129 "EventCode": "0x88",
130 "Counter": "0,1,2,3",
131 "UMask": "0xd0",
135 "CounterHTOff": "0,1,2,3,4,5,6,7"
138 "EventCode": "0x89",
139 "Counter": "0,1,2,3",
140 "UMask": "0x41",
144 "CounterHTOff": "0,1,2,3,4,5,6,7"
147 "EventCode": "0x89",
148 "Counter": "0,1,2,3",
149 "UMask": "0x81",
153 "CounterHTOff": "0,1,2,3,4,5,6,7"
156 "EventCode": "0x89",
157 "Counter": "0,1,2,3",
158 "UMask": "0x84",
162 "CounterHTOff": "0,1,2,3,4,5,6,7"
165 "EventCode": "0x89",
166 "Counter": "0,1,2,3",
167 "UMask": "0x88",
171 "CounterHTOff": "0,1,2,3,4,5,6,7"
174 "EventCode": "0x89",
175 "Counter": "0,1,2,3",
176 "UMask": "0x90",
180 "CounterHTOff": "0,1,2,3,4,5,6,7"
183 "EventCode": "0x89",
184 "Counter": "0,1,2,3",
185 "UMask": "0xa0",
189 "CounterHTOff": "0,1,2,3,4,5,6,7"
192 "EventCode": "0x89",
193 "Counter": "0,1,2,3",
194 "UMask": "0xc1",
198 "CounterHTOff": "0,1,2,3,4,5,6,7"
201 "EventCode": "0x89",
202 "Counter": "0,1,2,3",
203 "UMask": "0xc4",
207 "CounterHTOff": "0,1,2,3,4,5,6,7"
210 "EventCode": "0x89",
211 "Counter": "0,1,2,3",
212 "UMask": "0xd0",
216 "CounterHTOff": "0,1,2,3,4,5,6,7"
219 "EventCode": "0x3C",
220 "Counter": "0,1,2,3",
221 "UMask": "0x0",
225 "CounterHTOff": "0,1,2,3,4,5,6,7"
228 "EventCode": "0xA8",
229 "Counter": "0,1,2,3",
230 "UMask": "0x1",
234 "CounterHTOff": "0,1,2,3,4,5,6,7"
237 "EventCode": "0xA8",
238 "Counter": "0,1,2,3",
239 "UMask": "0x1",
244 "CounterHTOff": "0,1,2,3,4,5,6,7"
247 "EventCode": "0x87",
248 "Counter": "0,1,2,3",
249 "UMask": "0x1",
253 "CounterHTOff": "0,1,2,3,4,5,6,7"
256 "EventCode": "0x87",
257 "Counter": "0,1,2,3",
258 "UMask": "0x4",
262 "CounterHTOff": "0,1,2,3,4,5,6,7"
265 "EventCode": "0x0D",
266 "Counter": "0,1,2,3",
267 "UMask": "0x40",
271 "CounterHTOff": "0,1,2,3,4,5,6,7"
274 "EventCode": "0x59",
275 "Counter": "0,1,2,3",
276 "UMask": "0x20",
279 "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
280 "CounterHTOff": "0,1,2,3,4,5,6,7"
283 … where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and I…
284 "EventCode": "0x59",
285 "Counter": "0,1,2,3",
286 "UMask": "0x40",
290 "CounterHTOff": "0,1,2,3,4,5,6,7"
293 "EventCode": "0x59",
294 "Counter": "0,1,2,3",
295 "UMask": "0x80",
299 "CounterHTOff": "0,1,2,3,4,5,6,7"
302 "EventCode": "0xA2",
303 "Counter": "0,1,2,3",
304 "UMask": "0x1",
307 "BriefDescription": "Resource-related stall cycles.",
308 "CounterHTOff": "0,1,2,3,4,5,6,7"
311 "EventCode": "0xA2",
312 "Counter": "0,1,2,3",
313 "UMask": "0x2",
317 "CounterHTOff": "0,1,2,3,4,5,6,7"
320 "EventCode": "0xA2",
321 "Counter": "0,1,2,3",
322 "UMask": "0x4",
326 "CounterHTOff": "0,1,2,3,4,5,6,7"
329 "EventCode": "0xA2",
330 "Counter": "0,1,2,3",
331 "UMask": "0x8",
335 "CounterHTOff": "0,1,2,3,4,5,6,7"
338 "EventCode": "0xA2",
339 "Counter": "0,1,2,3",
340 "UMask": "0x10",
343 "BriefDescription": "Cycles stalled due to re-order buffer full.",
344 "CounterHTOff": "0,1,2,3,4,5,6,7"
347 "EventCode": "0x5B",
348 "Counter": "0,1,2,3",
349 "UMask": "0x40",
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
356 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
357 "EventCode": "0x0E",
358 "Counter": "0,1,2,3",
359 "UMask": "0x1",
363 "CounterHTOff": "0,1,2,3,4,5,6,7"
366 "EventCode": "0x0E",
368 "Counter": "0,1,2,3",
369 "UMask": "0x1",
374 "CounterHTOff": "0,1,2,3"
377 "EventCode": "0x0E",
379 "Counter": "0,1,2,3",
380 "UMask": "0x1",
386 "CounterHTOff": "0,1,2,3"
389 "EventCode": "0x5E",
390 "Counter": "0,1,2,3",
391 "UMask": "0x1",
395 "CounterHTOff": "0,1,2,3,4,5,6,7"
398 "EventCode": "0xCC",
399 "Counter": "0,1,2,3",
400 "UMask": "0x20",
404 "CounterHTOff": "0,1,2,3,4,5,6,7"
407 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
408 "EventCode": "0xC3",
409 "Counter": "0,1,2,3",
410 "UMask": "0x4",
413 "BriefDescription": "Self-modifying code (SMC) detected.",
414 "CounterHTOff": "0,1,2,3,4,5,6,7"
417 …ription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to in…
418 "EventCode": "0xC3",
419 "Counter": "0,1,2,3",
420 "UMask": "0x20",
423 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
424 "CounterHTOff": "0,1,2,3,4,5,6,7"
427 "EventCode": "0xC0",
428 "Counter": "0,1,2,3",
429 "UMask": "0x0",
432 … "BriefDescription": "Number of instructions retired. General Counter - architectural event.",
433 "CounterHTOff": "0,1,2,3,4,5,6,7"
437 "PublicDescription": "This event counts the number of micro-ops retired.",
438 "EventCode": "0xC2",
439 "Counter": "0,1,2,3",
440 "UMask": "0x1",
444 "CounterHTOff": "0,1,2,3,4,5,6,7"
448 …h cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in d…
449 "EventCode": "0xC2",
450 "Counter": "0,1,2,3",
451 "UMask": "0x2",
455 "CounterHTOff": "0,1,2,3,4,5,6,7"
458 "EventCode": "0xC2",
460 "Counter": "0,1,2,3",
461 "UMask": "0x1",
466 "CounterHTOff": "0,1,2,3"
469 "EventCode": "0xC2",
471 "Counter": "0,1,2,3",
472 "UMask": "0x1",
477 "CounterHTOff": "0,1,2,3"
481 "EventCode": "0xC4",
482 "Counter": "0,1,2,3",
483 "UMask": "0x1",
487 "CounterHTOff": "0,1,2,3,4,5,6,7"
491 "EventCode": "0xC4",
492 "Counter": "0,1,2,3",
493 "UMask": "0x2",
497 "CounterHTOff": "0,1,2,3,4,5,6,7"
500 "EventCode": "0xC4",
501 "Counter": "0,1,2,3",
502 "UMask": "0x0",
506 "CounterHTOff": "0,1,2,3,4,5,6,7"
510 "EventCode": "0xC4",
511 "Counter": "0,1,2,3",
512 "UMask": "0x8",
516 "CounterHTOff": "0,1,2,3,4,5,6,7"
519 "EventCode": "0xC4",
520 "Counter": "0,1,2,3",
521 "UMask": "0x10",
525 "CounterHTOff": "0,1,2,3,4,5,6,7"
529 "EventCode": "0xC4",
530 "Counter": "0,1,2,3",
531 "UMask": "0x20",
535 "CounterHTOff": "0,1,2,3,4,5,6,7"
538 "EventCode": "0xC4",
539 "Counter": "0,1,2,3",
540 "UMask": "0x40",
544 "CounterHTOff": "0,1,2,3,4,5,6,7"
547 "PEBS": "2",
548 "EventCode": "0xC4",
549 "Counter": "0,1,2,3",
550 "UMask": "0x4",
553 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
554 "CounterHTOff": "0,1,2,3"
558 "EventCode": "0xC5",
559 "Counter": "0,1,2,3",
560 "UMask": "0x1",
564 "CounterHTOff": "0,1,2,3,4,5,6,7"
568 "EventCode": "0xC5",
569 "Counter": "0,1,2,3",
570 "UMask": "0x2",
574 "CounterHTOff": "0,1,2,3,4,5,6,7"
577 "EventCode": "0xC5",
578 "Counter": "0,1,2,3",
579 "UMask": "0x0",
583 "CounterHTOff": "0,1,2,3,4,5,6,7"
587 "EventCode": "0xC5",
588 "Counter": "0,1,2,3",
589 "UMask": "0x10",
593 "CounterHTOff": "0,1,2,3,4,5,6,7"
597 "EventCode": "0xC5",
598 "Counter": "0,1,2,3",
599 "UMask": "0x20",
603 "CounterHTOff": "0,1,2,3,4,5,6,7"
606 "PEBS": "2",
607 … "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
608 "EventCode": "0xC5",
609 "Counter": "0,1,2,3",
610 "UMask": "0x4",
613 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
614 "CounterHTOff": "0,1,2,3"
617 "EventCode": "0xC1",
618 "Counter": "0,1,2,3",
619 "UMask": "0x2",
623 "CounterHTOff": "0,1,2,3,4,5,6,7"
626 "EventCode": "0x14",
627 "Counter": "0,1,2,3",
628 "UMask": "0x1",
632 "CounterHTOff": "0,1,2,3,4,5,6,7"
636 "EventCode": "0x14",
637 "Counter": "0,1,2,3",
638 "UMask": "0x1",
644 "CounterHTOff": "0,1,2,3,4,5,6,7"
647 "EventCode": "0xB1",
648 "Counter": "0,1,2,3",
649 "UMask": "0x1",
653 "CounterHTOff": "0,1,2,3,4,5,6,7"
656 "EventCode": "0xB1",
657 "Counter": "0,1,2,3",
658 "UMask": "0x2",
662 "CounterHTOff": "0,1,2,3,4,5,6,7"
665 "EventCode": "0xA1",
666 "Counter": "0,1,2,3",
667 "UMask": "0x1",
670 "BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
671 "CounterHTOff": "0,1,2,3,4,5,6,7"
674 "EventCode": "0xA1",
675 "Counter": "0,1,2,3",
676 "UMask": "0x2",
680 "CounterHTOff": "0,1,2,3,4,5,6,7"
683 "EventCode": "0xA1",
684 "Counter": "0,1,2,3",
685 "UMask": "0x40",
689 "CounterHTOff": "0,1,2,3,4,5,6,7"
692 "EventCode": "0xA1",
693 "Counter": "0,1,2,3",
694 "UMask": "0x80",
698 "CounterHTOff": "0,1,2,3,4,5,6,7"
701 "EventCode": "0xA3",
702 "Counter": "0,1,2,3",
703 "UMask": "0x4",
706 … no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be …
708 "CounterHTOff": "0,1,2,3"
711 "EventCode": "0xA3",
712 "Counter": "2",
713 "UMask": "0x2",
716 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
717 "CounterMask": "2",
718 "CounterHTOff": "2"
721 "EventCode": "0xA3",
722 "Counter": "0,1,2,3",
723 "UMask": "0x1",
726 …-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load…
728 "CounterHTOff": "0,1,2,3,4,5,6,7"
731 "EventCode": "0xA3",
732 "Counter": "2",
733 "UMask": "0x6",
736 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
738 "CounterHTOff": "2"
741 "EventCode": "0xA3",
742 "Counter": "0,1,2,3",
743 "UMask": "0x5",
746 …-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry…
748 "CounterHTOff": "0,1,2,3"
751 "EventCode": "0x4C",
752 "Counter": "0,1,2,3",
753 "UMask": "0x1",
756 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
757 "CounterHTOff": "0,1,2,3,4,5,6,7"
760 "EventCode": "0x4C",
761 "Counter": "0,1,2,3",
762 "UMask": "0x2",
765 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
766 "CounterHTOff": "0,1,2,3,4,5,6,7"
769 "EventCode": "0x03",
770 "Counter": "0,1,2,3",
771 "UMask": "0x1",
775 "CounterHTOff": "0,1,2,3,4,5,6,7"
778 …tore. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Opti…
779 "EventCode": "0x03",
780 "Counter": "0,1,2,3",
781 "UMask": "0x2",
784 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
785 "CounterHTOff": "0,1,2,3,4,5,6,7"
788 "EventCode": "0x03",
789 "Counter": "0,1,2,3",
790 "UMask": "0x8",
794 "CounterHTOff": "0,1,2,3,4,5,6,7"
797 "EventCode": "0x03",
798 "Counter": "0,1,2,3",
799 "UMask": "0x10",
802 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
803 "CounterHTOff": "0,1,2,3,4,5,6,7"
807 "EventCode": "0x07",
808 "Counter": "0,1,2,3",
809 "UMask": "0x1",
813 "CounterHTOff": "0,1,2,3,4,5,6,7"
816 "EventCode": "0x07",
817 "Counter": "0,1,2,3",
818 "UMask": "0x8",
822 "CounterHTOff": "0,1,2,3,4,5,6,7"
825 "EventCode": "0xB6",
826 "Counter": "0,1,2,3",
827 "UMask": "0x1",
830 …with all the following traits: 1. addressing of the format [base + offset], 2. the offset is betwe…
831 "CounterHTOff": "0,1,2,3,4,5,6,7"
834 "EventCode": "0x3C",
835 "Counter": "0,1,2,3",
836 "UMask": "0x1",
840 "CounterHTOff": "0,1,2,3,4,5,6,7"
843 "EventCode": "0x3C",
844 "Counter": "0,1,2,3",
845 "UMask": "0x2",
849 "CounterHTOff": "0,1,2,3"
852 "EventCode": "0xA1",
853 "Counter": "0,1,2,3",
854 "UMask": "0x1",
858 "BriefDescription": "Cycles per core when uops are dispatched to port 0.",
859 "CounterHTOff": "0,1,2,3,4,5,6,7"
862 "EventCode": "0xA1",
863 "Counter": "0,1,2,3",
864 "UMask": "0x2",
869 "CounterHTOff": "0,1,2,3,4,5,6,7"
872 "EventCode": "0xA1",
873 "Counter": "0,1,2,3",
874 "UMask": "0x40",
879 "CounterHTOff": "0,1,2,3,4,5,6,7"
882 "EventCode": "0xA1",
883 "Counter": "0,1,2,3",
884 "UMask": "0x80",
889 "CounterHTOff": "0,1,2,3,4,5,6,7"
892 "EventCode": "0xA1",
893 "Counter": "0,1,2,3",
894 "UMask": "0xc",
897 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
898 "CounterHTOff": "0,1,2,3,4,5,6,7"
901 "EventCode": "0xA1",
902 "Counter": "0,1,2,3",
903 "UMask": "0x30",
907 "CounterHTOff": "0,1,2,3,4,5,6,7"
910 "EventCode": "0xA1",
911 "Counter": "0,1,2,3",
912 "UMask": "0xc",
916 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
917 "CounterHTOff": "0,1,2,3,4,5,6,7"
920 "EventCode": "0xA1",
921 "Counter": "0,1,2,3",
922 "UMask": "0x30",
927 "CounterHTOff": "0,1,2,3,4,5,6,7"
930 "PEBS": "2",
931 "EventCode": "0xC0",
933 "UMask": "0x1",
936 "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
941 "EventCode": "0x5B",
942 "Counter": "0,1,2,3",
943 "UMask": "0xf",
947 "CounterHTOff": "0,1,2,3,4,5,6,7"
950 "EventCode": "0x5B",
951 "Counter": "0,1,2,3",
952 "UMask": "0xc",
956 "CounterHTOff": "0,1,2,3,4,5,6,7"
959 "EventCode": "0xA2",
960 "Counter": "0,1,2,3",
961 "UMask": "0xe",
965 "CounterHTOff": "0,1,2,3,4,5,6,7"
968 "EventCode": "0xA2",
969 "Counter": "0,1,2,3",
970 "UMask": "0xf0",
974 "CounterHTOff": "0,1,2,3,4,5,6,7"
977 "EventCode": "0x5B",
978 "Counter": "0,1,2,3",
979 "UMask": "0x4f",
983 "CounterHTOff": "0,1,2,3,4,5,6,7"
986 "EventCode": "0xA2",
987 "Counter": "0,1,2,3",
988 "UMask": "0xa",
992 "CounterHTOff": "0,1,2,3,4,5,6,7"
995 "EventCode": "0x0D",
996 "Counter": "0,1,2,3",
997 "UMask": "0x3",
1002 "CounterHTOff": "0,1,2,3,4,5,6,7"
1005 …cuting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mo…
1006 "EventCode": "0x59",
1007 "Counter": "0,1,2,3",
1008 "UMask": "0x20",
1011 … "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
1013 "CounterHTOff": "0,1,2,3,4,5,6,7"
1016 "EventCode": "0x0D",
1017 "Counter": "0,1,2,3",
1018 "UMask": "0x3",
1024 "CounterHTOff": "0,1,2,3,4,5,6,7"
1027 "EventCode": "0xE6",
1028 "Counter": "0,1,2,3",
1029 "UMask": "0x1f",
1033 "CounterHTOff": "0,1,2,3,4,5,6,7"
1036 "EventCode": "0x88",
1037 "Counter": "0,1,2,3",
1038 "UMask": "0xff",
1042 "CounterHTOff": "0,1,2,3,4,5,6,7"
1045 "EventCode": "0x89",
1046 "Counter": "0,1,2,3",
1047 "UMask": "0xff",
1051 "CounterHTOff": "0,1,2,3,4,5,6,7"
1054 "EventCode": "0xC2",
1056 "Counter": "0,1,2,3",
1057 "UMask": "0x1",
1062 "CounterHTOff": "0,1,2,3"
1065 "EventCode": "0xA8",
1066 "Counter": "0,1,2,3",
1067 "UMask": "0x1",
1072 "CounterHTOff": "0,1,2,3,4,5,6,7"
1075 "EventCode": "0xc3",
1076 "Counter": "0,1,2,3",
1077 "UMask": "0x1",
1083 "CounterHTOff": "0,1,2,3,4,5,6,7"
1086 "EventCode": "0x5E",
1088 "Counter": "0,1,2,3",
1089 "UMask": "0x1",
1095 "CounterHTOff": "0,1,2,3,4,5,6,7"
1098 "Counter": "Fixed counter 2",
1099 "UMask": "0x2",
1104 "CounterHTOff": "Fixed counter 2"
1107 "EventCode": "0x3C",
1108 "Counter": "0,1,2,3",
1109 "UMask": "0x0",
1114 "CounterHTOff": "0,1,2,3,4,5,6,7"
1117 "EventCode": "0x3C",
1118 "Counter": "0,1,2,3",
1119 "UMask": "0x1",
1124 "CounterHTOff": "0,1,2,3,4,5,6,7"
1127 "EventCode": "0x0D",
1128 "Counter": "0,1,2,3",
1129 "UMask": "0x3",
1135 "CounterHTOff": "0,1,2,3,4,5,6,7"
1138 "EventCode": "0xB1",
1139 "Counter": "0,1,2,3",
1140 "UMask": "0x2",
1143 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1145 "CounterHTOff": "0,1,2,3,4,5,6,7"
1148 "EventCode": "0xB1",
1149 "Counter": "0,1,2,3",
1150 "UMask": "0x2",
1153 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1154 "CounterMask": "2",
1155 "CounterHTOff": "0,1,2,3,4,5,6,7"
1158 "EventCode": "0xB1",
1159 "Counter": "0,1,2,3",
1160 "UMask": "0x2",
1163 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1165 "CounterHTOff": "0,1,2,3,4,5,6,7"
1168 "EventCode": "0xB1",
1169 "Counter": "0,1,2,3",
1170 "UMask": "0x2",
1173 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1175 "CounterHTOff": "0,1,2,3,4,5,6,7"
1178 "EventCode": "0xB1",
1180 "Counter": "0,1,2,3",
1181 "UMask": "0x2",
1184 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1185 "CounterHTOff": "0,1,2,3,4,5,6,7"
1189 "EventCode": "0x3C",
1190 "Counter": "0,1,2,3",
1191 "UMask": "0x1",
1195 "CounterHTOff": "0,1,2,3,4,5,6,7"
1198 "EventCode": "0x3C",
1199 "Counter": "0,1,2,3",
1200 "UMask": "0x1",
1205 "CounterHTOff": "0,1,2,3,4,5,6,7"
1208 "EventCode": "0x3C",
1209 "Counter": "0,1,2,3",
1210 "UMask": "0x2",
1214 "CounterHTOff": "0,1,2,3,4,5,6,7"