| /Linux-v5.15/drivers/pwm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig PWM config
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
14 This framework provides a generic interface to PWM devices
16 to register and unregister a PWM chip, an abstraction of a PWM
17 controller, that supports one or more PWM devices. Client
18 drivers can request PWM devices and use the generic framework
21 This generic framework replaces the legacy PWM framework which
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| D | core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2011-2012 Avionic Design GmbH
11 #include <linux/pwm.h>
12 #include <linux/radix-tree.h>
21 #include <dt-bindings/pwm/pwm.h>
24 #include <trace/events/pwm.h>
35 static struct pwm_device *pwm_to_device(unsigned int pwm) in pwm_to_device() argument
37 return radix_tree_lookup(&pwm_tree, pwm); in pwm_to_device()
48 return -ENOSPC; in alloc_pwms()
57 for (i = 0; i < chip->npwm; i++) { in free_pwms()
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PWM) += core.o
3 obj-$(CONFIG_PWM_SYSFS) += sysfs.o
4 obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
5 obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
6 obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
7 obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
8 obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
9 obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
10 obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
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| D | pwm-renesas-tpu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
18 #include <linux/pwm.h>
63 TPU_PIN_PWM, /* Pin is driven by PWM */
92 static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value) in tpu_pwm_write() argument
94 void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET in tpu_pwm_write()
95 + pwm->channel * TPU_CHANNEL_SIZE; in tpu_pwm_write()
100 static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm, in tpu_pwm_set_pin() argument
103 static const char * const states[] = { "inactive", "PWM", "active" }; in tpu_pwm_set_pin()
105 dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n", in tpu_pwm_set_pin()
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| D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
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| D | pwm-twl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pwm.h>
32 #define TWL4030_PWM_TOGGLE(pwm, x) ((x) << (pwm)) argument
46 #define TWL6030_PWM_TOGGLE(pwm, x) ((x) << (pwm * 3)) argument
60 static int twl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in twl_pwm_config() argument
69 * On-cycle is set to 1 (the minimum allowed value) in twl_pwm_config()
71 * 0 -> off cycle = 2, in twl_pwm_config()
72 * 1 -> off cycle = 2, in twl_pwm_config()
73 * 2 -> off cycle = 3, in twl_pwm_config()
74 * 126 - > off cycle 127, in twl_pwm_config()
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| D | pwm-sun4i.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
22 #include <linux/pwm.h>
48 #define PWM_PRD(prd) (((prd) - 1) << 16)
103 return readl(chip->base + offset); in sun4i_pwm_readl()
109 writel(val, chip->base + offset); in sun4i_pwm_writel()
113 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
121 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
126 * PWM chapter in H6 manual has a diagram which explains that if bypass in sun4i_pwm_get_state()
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| D | sysfs.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * A simple sysfs interface for the generic PWM framework
15 #include <linux/pwm.h>
19 struct pwm_device *pwm; member
33 return export->pwm; in child_to_pwm_device()
40 const struct pwm_device *pwm = child_to_pwm_device(child); in period_show() local
43 pwm_get_state(pwm, &state); in period_show()
53 struct pwm_device *pwm = export->pwm; in period_store() local
62 mutex_lock(&export->lock); in period_store()
63 pwm_get_state(pwm, &state); in period_store()
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| D | pwm-lpss.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Low Power Subsystem PWM controller driver
21 #include "pwm-lpss.h"
23 #define PWM 0x00000000 macro
29 /* Size of each PWM register space if multiple */
37 static inline u32 pwm_lpss_read(const struct pwm_device *pwm) in pwm_lpss_read() argument
39 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); in pwm_lpss_read()
41 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_read()
44 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) in pwm_lpss_write() argument
46 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); in pwm_lpss_write()
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| D | pwm-stmpe.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pwm.h>
39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument
45 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS); in stmpe_24xx_pwm_enable()
47 dev_err(chip->dev, "error reading PWM#%u control\n", in stmpe_24xx_pwm_enable()
48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
54 ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value); in stmpe_24xx_pwm_enable()
56 dev_err(chip->dev, "error writing PWM#%u control\n", in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
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| D | pwm-img.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2015, Imagination Technologies
7 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
19 #include <linux/pwm.h>
23 /* PWM registers */
43 * PWM period is specified with a timebase register,
44 * in number of step periods. The PWM duty cycle is also
49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
83 writel(val, chip->base + reg); in img_pwm_writel()
89 return readl(chip->base + reg); in img_pwm_readl()
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| D | pwm-jz4740.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
41 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2); in jz4740_pwm_can_use_chn()
43 device_property_read_u32(jz->chip.dev->parent, in jz4740_pwm_can_use_chn()
44 "ingenic,pwm-channels-mask", in jz4740_pwm_can_use_chn()
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| /Linux-v5.15/include/linux/ |
| D | pwm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * enum pwm_polarity - polarity of a PWM signal
16 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
19 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
29 * struct pwm_args - board-dependent PWM arguments
33 * This structure describes board-dependent arguments attached to a PWM
34 * device. These arguments are usually retrieved from the PWM lookup table or
37 * Do not confuse this with the PWM state: PWM arguments represent the initial
38 * configuration that users want to use on this PWM device rather than the
39 * current PWM hardware state.
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| /Linux-v5.15/Documentation/devicetree/bindings/pwm/ |
| D | pwm.txt | 1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
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| D | renesas,pwm-rcar.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car PWM Timer Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
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| D | pwm-samsung.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
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| D | imx-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX PWM controller
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 "#pwm-cells":
15 Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
18 - 2
19 - 3
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| D | pwm-rockchip.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PWM controller
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
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| D | allwinner,sun4i-a10-pwm.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 PWM Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
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| D | nvidia,tegra20-pwm.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - "nvidia,tegra194-pwm": for Tegra194
13 - reg: physical base address and length of the controller's registers
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| D | pwm-sifive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 Unlike most other PWM controllers, the SiFive PWM controller currently
17 only supports one period for all channels in the PWM. All PWMs need to
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| D | pwm-mediatek.txt | 1 MediaTek PWM controller
4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt7622-pwm": found on mt7622 SoC.
7 - "mediatek,mt7623-pwm": found on mt7623 SoC.
8 - "mediatek,mt7628-pwm": found on mt7628 SoC.
9 - "mediatek,mt7629-pwm": found on mt7629 SoC.
10 - "mediatek,mt8183-pwm": found on mt8183 SoC.
11 - "mediatek,mt8516-pwm": found on mt8516 SoC.
12 - reg: physical base address and length of the controller's registers.
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| /Linux-v5.15/drivers/clocksource/ |
| D | samsung_pwm_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * samsung - Common hr-timer support (s3c and s5p)
79 static struct samsung_pwm_clocksource pwm; variable
92 reg = readl(pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
94 reg |= (prescale - 1) << shift; in samsung_timer_set_prescale()
95 writel(reg, pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
107 bits = (fls(divisor) - 1) - pwm.variant.div_base; in samsung_timer_set_divisor()
111 reg = readl(pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
114 writel(reg, pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
129 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_stop()
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| /Linux-v5.15/Documentation/driver-api/ |
| D | pwm.rst | 2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
15 ----------------
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
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| /Linux-v5.15/Documentation/ABI/testing/ |
| D | sysfs-class-pwm | 1 What: /sys/class/pwm/
6 The pwm/ class sub-directory belongs to the Generic PWM
7 Framework and provides a sysfs interface for using PWM
10 What: /sys/class/pwm/pwmchipN/
15 A /sys/class/pwm/pwmchipN directory is created for each
16 probed PWM controller/chip where N is the base of the
17 PWM chip.
19 What: /sys/class/pwm/pwmchipN/npwm
24 The number of PWM channels supported by the PWM chip.
26 What: /sys/class/pwm/pwmchipN/export
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