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/Linux-v5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h265 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W()
267 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG()
287 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R()
289 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG()
319 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC()
321 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + _… in REG_MDP5_IGC_LUT()
323 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000… in REG_MDP5_IGC_LUT_REG()
360 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL()
374 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_… in REG_MDP5_CTL_LAYER()
376 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off… in REG_MDP5_CTL_LAYER_REG()
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/Linux-v5.10/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h319 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP()
321 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG()
323 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE()
337 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE()
339 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE()
341 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE()
353 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset… in REG_MDP4_OVLP_STAGE()
355 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __off… in REG_MDP4_OVLP_STAGE_OP()
375 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 +… in REG_MDP4_OVLP_STAGE_FG_ALPHA()
377 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 +… in REG_MDP4_OVLP_STAGE_BG_ALPHA()
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/Linux-v5.10/drivers/gpu/drm/etnaviv/
Dstate.xml.h73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) argument
192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
196 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) argument
198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) argument
200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) argument
204 #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) argument
206 #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) argument
208 #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) argument
210 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) argument
214 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) argument
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Dstate_hi.xml.h340 #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) argument
352 #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) argument
/Linux-v5.10/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h415 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK()
417 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA()
731 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
733 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
735 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
737 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
739 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
741 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
743 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
960 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN()
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Dmmss_cc.xml.h64 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0);… in REG_MMSS_CC_CLK()
66 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i… in REG_MMSS_CC_CLK_CC()
83 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i… in REG_MMSS_CC_CLK_MD()
97 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i… in REG_MMSS_CC_CLK_NS()
/Linux-v5.10/drivers/gpu/drm/msm/adreno/
Da4xx.xml.h970 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT()
972 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL()
990 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } in REG_A4XX_RB_MRT_BUF_INFO()
1023 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } in REG_A4XX_RB_MRT_BASE()
1025 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL3()
1033 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } in REG_A4XX_RB_MRT_BLEND_CONTROL()
1536 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP()
1538 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MIN()
1540 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MAX()
1546 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_TP()
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Da6xx.xml.h1068 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH()
1070 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG()
1072 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT()
1074 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG()
2622 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } in REG_A6XX_VSC_PIPE_CONFIG()
2624 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } in REG_A6XX_VSC_PIPE_CONFIG_REG()
2670 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } in REG_A6XX_VSC_STATE()
2672 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } in REG_A6XX_VSC_STATE_REG()
2674 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } in REG_A6XX_VSC_PRIM_STRM_SIZE()
2676 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } in REG_A6XX_VSC_PRIM_STRM_SIZE_REG()
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Da3xx.xml.h915 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT()
917 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT_REG()
1221 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT()
1223 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT_CONTROL()
1246 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_INFO()
1273 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_BASE()
1281 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } in REG_A3XX_RB_MRT_BLEND_CONTROL()
1880 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK()
1882 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0;… in REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE()
1884 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i… in REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET()
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Da5xx.xml.h1033 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH()
1035 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH_REG()
1037 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT()
1039 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT_REG()
2131 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } in REG_A5XX_VSC_PIPE_CONFIG()
2133 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } in REG_A5XX_VSC_PIPE_CONFIG_REG()
2159 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } in REG_A5XX_VSC_PIPE_DATA_ADDRESS()
2161 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0;… in REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO()
2163 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0;… in REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI()
2165 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } in REG_A5XX_VSC_PIPE_DATA_LENGTH()
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Dadreno_pm4.xml.h1071 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE_()
1073 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__0()
1094 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__1()
1102 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__2()
2125 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG_()
2127 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__0()
2135 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__1()
2143 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__2()
Da2xx.xml.h1424 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } in REG_A2XX_VSC_PIPE()
1426 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } in REG_A2XX_VSC_PIPE_CONFIG()
1428 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } in REG_A2XX_VSC_PIPE_DATA_ADDRESS()
1430 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } in REG_A2XX_VSC_PIPE_DATA_LENGTH()
/Linux-v5.10/tools/testing/selftests/proc/
Dproc-uptime-001.c28 uint64_t start, u0, u1, i0, i1; in main() local
Dproc-uptime-002.c47 uint64_t u0, u1, i0, i1; in main() local
/Linux-v5.10/fs/jffs2/
Dcompr_rubin.c105 long i0, i1; in encode() local
203 long i0, threshold; in decode() local
/Linux-v5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h171 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } in REG_HDMI_AVI_INFO()
175 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } in REG_HDMI_GENERIC0()
179 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } in REG_HDMI_GENERIC1()
181 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR()
183 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR_0()
191 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } in REG_HDMI_ACR_1()
388 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION()
390 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION_REG()
/Linux-v5.10/lib/crypto/
Dcurve25519-hacl64.c195 u64 i0; in fmul_fmul() local
253 u64 i0; in fsquare_fsquare_() local
609 u64 i0, i1, i2, i3, i4, output0, output1, output2, output3, output4; in format_fexpand() local
679 u64 i0; in format_fcontract_second_carry_full() local
/Linux-v5.10/drivers/gpu/drm/msm/edp/
Dedp.xml.h276 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } in REG_EDP_PHY_LN()
278 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } in REG_EDP_PHY_LN_PD_CTL()
/Linux-v5.10/arch/powerpc/sysdev/xive/
Dcommon.c230 u32 i0, i1, idx; in xive_dump_eq() local
1587 u32 i0, i1, idx; in xive_debug_show_cpu() local
/Linux-v5.10/drivers/soc/qcom/
Docmem.c87 #define OCMEM_REG_PSGSC_CTL(i0) (0x0000003c + 0x1*(i0)) argument
/Linux-v5.10/sound/pci/cs46xx/
Dcs46xx_dsp_scb_types.h1110 u32 i0; member
/Linux-v5.10/arch/powerpc/kvm/
Dbook3s_xive.c2123 u32 i0, i1, idx; in kvmppc_xive_debug_show_queues() local
/Linux-v5.10/drivers/gpu/drm/savage/
Dsavage_drv.h477 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ argument
/Linux-v5.10/fs/jfs/
Djfs_dmap.c3375 int i, i0 = true, j, j0 = true, k, n; in dbExtendFS() local
/Linux-v5.10/drivers/gpu/drm/nouveau/include/nvif/
Dpush.h91 #define PUSH_DATA_(X,p,m,i0,i1,d,s,f,a...) PUSH_DATA__((p), (d), "-> "#m f, ##a) argument