| /Linux-v6.6/drivers/gpu/drm/i915/display/ |
| D | intel_ddi_buf_trans.c | 1306 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1335 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1360 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1385 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1412 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1431 if (crtc_state->port_clock > 540000) { in tgl_get_combo_buf_trans_edp()
1463 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1476 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1507 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1518 if (crtc_state->port_clock > 540000) { in rkl_get_combo_buf_trans_edp()
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| D | intel_dpll.c | 772 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
1016 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); in mtl_crtc_compute_clock()
1018 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20); in mtl_crtc_compute_clock()
1178 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1189 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1252 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1262 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1277 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1288 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1326 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
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| D | intel_pmdemand.c | 135 enum pipe pipe, int port_clock) in intel_pmdemand_update_port_clock() argument
140 pmdemand_state->ddi_clocks[pipe] = port_clock; in intel_pmdemand_update_port_clock()
156 new_crtc_state->port_clock); in intel_pmdemand_update_max_ddiclk()
300 if (new_crtc_state->port_clock != old_crtc_state->port_clock) in intel_pmdemand_needs_update()
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| D | intel_pmdemand.h | 56 enum pipe pipe, int port_clock);
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| D | intel_dp_link_training.c | 681 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, in intel_dp_prepare_link_train()
878 } else if (crtc_state->port_clock == 810000) { in intel_dp_training_pattern()
896 } else if (crtc_state->port_clock >= 540000) { in intel_dp_training_pattern()
1058 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1079 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
1325 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_128b132b_link_train()
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| D | g4x_dp.c | 79 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
98 pipe_config->port_clock, in intel_dp_prepare()
201 pipe_config->port_clock); in ilk_edp_pll_on()
205 if (pipe_config->port_clock == 162000) in ilk_edp_pll_on()
387 pipe_config->port_clock = 162000; in intel_dp_get_config()
389 pipe_config->port_clock = 270000; in intel_dp_get_config()
393 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
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| D | intel_ddi.c | 264 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
299 static u32 ddi_buf_phy_link_rate(int port_clock) in ddi_buf_phy_link_rate() argument
301 switch (port_clock) { in ddi_buf_phy_link_rate()
319 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
345 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
1098 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1294 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
1302 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1309 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
2416 crtc_state->port_clock, in mtl_ddi_pre_enable_dp()
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| D | intel_cx0_phy.c | 332 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
333 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
346 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
347 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
1797 if (crtc_state->port_clock == tables[i]->clock) { in intel_c10pll_calc_state()
2022 if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, in intel_c20pll_calc_state()
2032 if (crtc_state->port_clock == tables[i]->link_bit_rate) { in intel_c20pll_calc_state()
2423 if (is_hdmi_frl(crtc_state->port_clock)) in intel_program_port_clock_ctl()
2430 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) in intel_program_port_clock_ctl()
2745 crtc_state->port_clock); in intel_cx0pll_enable()
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| D | intel_dpll_mgr.c | 970 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_compute_dpll()
977 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
1000 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1020 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1076 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_compute_dpll()
1716 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, in skl_ddi_hdmi_pll_dividers()
1735 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1751 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2156 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2165 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
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| D | intel_dp_mst.c | 56 int symbol_clock = crtc_state->port_clock / 32; in intel_dp_mst_check_constraints()
95 crtc_state->port_clock = limits->max_rate; in intel_dp_mst_find_vcpi_slots_for_bpp()
100 crtc_state->port_clock, in intel_dp_mst_find_vcpi_slots_for_bpp()
169 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
263 crtc_state->port_clock, in intel_dp_dsc_mst_compute_link_config()
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| D | intel_dp.h | 84 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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| D | intel_dpio_phy.c | 942 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
944 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
946 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
948 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
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| D | intel_audio.c | 145 crtc_state->port_clock == dp_aud_n_m[i].clock) in audio_config_dp_get_n_m()
302 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
535 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
573 link_clk = crtc_state->port_clock; in calc_samples_room()
852 crtc_state->port_clock, in intel_audio_codec_enable()
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| D | vlv_dsi_pll.c | 203 config->port_clock = pclk; in vlv_dsi_pll_compute()
526 config->port_clock = pclk; in bxt_dsi_pll_compute()
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| D | intel_dp.c | 127 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
1285 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, in intel_dp_compute_rate() argument
1292 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1294 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1504 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1700 pipe_config->port_clock = limits->max_rate; in intel_dp_dsc_compute_config()
1722 pipe_config->port_clock, in intel_dp_dsc_compute_config()
1873 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1881 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1885 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
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| D | g4x_hdmi.c | 190 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); in intel_hdmi_get_config()
192 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
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| D | intel_tv.c | 1122 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1149 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1215 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
1223 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); in intel_tv_compute_config()
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| D | intel_display.c | 2814 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
2848 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
3009 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
3843 int port_clock; in i9xx_crtc_clock_get() local
3885 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
3887 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
3916 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
3924 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
3952 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in intel_crtc_dotclock()
3955 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
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| D | intel_crt.c | 147 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
452 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
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| D | intel_modeset_setup.c | 556 crtc_state->port_clock == 0; in has_bogus_dpll_config()
872 crtc_state->port_clock); in intel_modeset_readout_hw_state()
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| D | intel_crtc_state_dump.c | 316 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), in intel_crtc_state_dump()
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| D | intel_dvo.c | 178 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
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| D | intel_snps_phy.c | 1793 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) in intel_mpllb_calc_state()
1801 crtc_state->port_clock); in intel_mpllb_calc_state()
1811 if (crtc_state->port_clock == tables[i]->clock) { in intel_mpllb_calc_state()
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| D | intel_lvds.c | 156 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_lvds_get_config()
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| D | intel_cdclk.c | 2558 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2585 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2829 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
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