Searched refs:component_reg_phys (Results 1 – 10 of 10) sorted by relevance
| /Linux-v6.6/drivers/cxl/core/ |
| D | port.c | 622 resource_size_t component_reg_phys, in cxl_port_alloc() argument
673 port->component_reg_phys = component_reg_phys; in cxl_port_alloc()
695 resource_size_t component_reg_phys) in cxl_setup_comp_regs() argument
697 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_setup_comp_regs()
703 .resource = component_reg_phys, in cxl_setup_comp_regs()
711 resource_size_t component_reg_phys) in cxl_port_setup_regs() argument
716 component_reg_phys); in cxl_port_setup_regs()
720 resource_size_t component_reg_phys) in cxl_dport_setup_regs() argument
725 component_reg_phys); in cxl_dport_setup_regs()
730 resource_size_t component_reg_phys, in __devm_cxl_add_port() argument
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| D | regs.c | 476 resource_size_t component_reg_phys; in __rcrb_to_component() local
523 component_reg_phys = bar0 & PCI_BASE_ADDRESS_MEM_MASK; in __rcrb_to_component()
525 component_reg_phys |= ((u64)bar1) << 32; in __rcrb_to_component()
527 if (!component_reg_phys) in __rcrb_to_component()
531 if (!IS_ALIGNED(component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE)) in __rcrb_to_component()
534 return component_reg_phys; in __rcrb_to_component()
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| D | hdm.c | 89 .resource = port->component_reg_phys, in map_hdm_decoder_regs()
167 crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE); in devm_cxl_setup_hdm()
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| /Linux-v6.6/tools/testing/cxl/test/ |
| D | mock.c | 275 resource_size_t component_reg_phys; in __wrap_cxl_rcd_component_reg_phys() local
279 component_reg_phys = CXL_RESOURCE_NONE; in __wrap_cxl_rcd_component_reg_phys()
281 component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); in __wrap_cxl_rcd_component_reg_phys()
284 return component_reg_phys; in __wrap_cxl_rcd_component_reg_phys()
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| D | mem.c | 1426 cxlds->component_reg_phys = CXL_RESOURCE_NONE; in cxl_mock_mem_probe()
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| /Linux-v6.6/drivers/cxl/ |
| D | acpi.c | 457 resource_size_t component_reg_phys; in add_host_bridge_uport() local
486 component_reg_phys = ctx.base; in add_host_bridge_uport()
487 if (component_reg_phys != CXL_RESOURCE_NONE) in add_host_bridge_uport()
489 ctx.uid, &component_reg_phys); in add_host_bridge_uport()
495 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport); in add_host_bridge_uport()
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| D | pci.c | 484 resource_size_t component_reg_phys; in cxl_rcrb_get_comp_regs() local
495 component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); in cxl_rcrb_get_comp_regs()
499 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_rcrb_get_comp_regs()
502 map->resource = component_reg_phys; in cxl_rcrb_get_comp_regs()
837 cxlds->component_reg_phys = CXL_RESOURCE_NONE; in cxl_pci_probe()
844 cxlds->component_reg_phys = map.resource; in cxl_pci_probe()
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| D | cxl.h | 599 resource_size_t component_reg_phys; member
690 resource_size_t component_reg_phys,
704 resource_size_t component_reg_phys);
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| D | mem.c | 69 cxlds->component_reg_phys, in devm_cxl_add_endpoint()
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| D | cxlmem.h | 421 resource_size_t component_reg_phys; member
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