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Searched refs:REG_CLR_FLD (Results 1 – 3 of 3) sorted by relevance

/Linux-v6.6/drivers/accel/ivpu/
Divpu_hw_37xx.c291 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); in ivpu_boot_host_ss_rst_drive()
292 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
293 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
308 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in ivpu_boot_host_ss_clk_drive()
309 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
310 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
400 val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in ivpu_boot_host_ss_axi_drive()
431 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
432 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
461 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in ivpu_boot_pwr_island_trickle_drive()
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Divpu_hw_40xx.c273 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in ivpu_boot_host_ss_rst_drive()
274 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
275 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
290 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in ivpu_boot_host_ss_clk_drive()
291 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
292 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
368 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in ivpu_boot_idle_gen_drive()
405 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in ivpu_boot_host_ss_axi_drive()
443 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
444 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
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Divpu_hw_reg_io.h39 #define REG_CLR_FLD(REG, FLD, val) \ macro