273 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);  in ivpu_boot_host_ss_rst_drive()
274 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);  in ivpu_boot_host_ss_rst_drive()
275 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);  in ivpu_boot_host_ss_rst_drive()
290 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);  in ivpu_boot_host_ss_clk_drive()
291 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);  in ivpu_boot_host_ss_clk_drive()
292 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);  in ivpu_boot_host_ss_clk_drive()
368 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);  in ivpu_boot_idle_gen_drive()
405 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);  in ivpu_boot_host_ss_axi_drive()
443 		val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);  in ivpu_boot_host_ss_top_noc_drive()
444 		val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);  in ivpu_boot_host_ss_top_noc_drive()
473 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);  in ivpu_boot_pwr_island_trickle_drive()
488 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);  in ivpu_boot_pwr_island_drive()
512 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);  in ivpu_boot_pwr_island_isolation_drive()
522 	val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);  in ivpu_boot_no_snoop_enable()
523 	val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);  in ivpu_boot_no_snoop_enable()
603 		val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);  in ivpu_boot_soc_cpu_drive()
665 		val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);  in ivpu_boot_d0i3_drive()
791 		val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);  in ivpu_hw_40xx_profiling_freq_reg_set()
925 	val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);  in ivpu_hw_40xx_wdt_disable()