Searched refs:REGV_RD32 (Results 1 – 4 of 4) sorted by relevance
87 u32 gen_ctrl = REGV_RD32(VPU_37XX_HOST_SS_GEN_CTRL); in ivpu_hw_read_platform()284 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); in ivpu_boot_host_ss_rst_drive()301 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); in ivpu_boot_host_ss_clk_drive()318 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in ivpu_boot_noc_qreqn_check()328 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); in ivpu_boot_noc_qacceptn_check()338 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); in ivpu_boot_noc_qdeny_check()348 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN); in ivpu_boot_top_noc_qrenqn_check()359 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QACCEPTN); in ivpu_boot_top_noc_qacceptn_check()370 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QDENY); in ivpu_boot_top_noc_qdeny_check()396 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in ivpu_boot_host_ss_axi_drive()[all …]
266 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); in ivpu_boot_host_ss_rst_drive()283 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); in ivpu_boot_host_ss_clk_drive()300 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in ivpu_boot_noc_qreqn_check()310 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); in ivpu_boot_noc_qacceptn_check()320 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); in ivpu_boot_noc_qdeny_check()330 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in ivpu_boot_top_noc_qrenqn_check()341 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); in ivpu_boot_top_noc_qacceptn_check()352 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); in ivpu_boot_top_noc_qdeny_check()363 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); in ivpu_boot_idle_gen_drive()401 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in ivpu_boot_host_ss_axi_drive()[all …]
253 val = REGV_RD32(VPU_37XX_HOST_MMU_IDR0); in ivpu_mmu_config_check()257 val = REGV_RD32(VPU_37XX_HOST_MMU_IDR1); in ivpu_mmu_config_check()261 val = REGV_RD32(VPU_37XX_HOST_MMU_IDR3); in ivpu_mmu_config_check()272 val = REGV_RD32(VPU_37XX_HOST_MMU_IDR5); in ivpu_mmu_config_check()804 evtq->prod = REGV_RD32(VPU_37XX_HOST_MMU_EVTQ_PROD_SEC); in ivpu_mmu_get_event()844 gerror_val = REGV_RD32(VPU_37XX_HOST_MMU_GERROR); in ivpu_mmu_irq_gerr_handler()845 gerrorn_val = REGV_RD32(VPU_37XX_HOST_MMU_GERRORN); in ivpu_mmu_irq_gerr_handler()
24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__) macro
