266 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);  in ivpu_boot_host_ss_rst_drive()
283 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);  in ivpu_boot_host_ss_clk_drive()
300 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);  in ivpu_boot_noc_qreqn_check()
310 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);  in ivpu_boot_noc_qacceptn_check()
320 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);  in ivpu_boot_noc_qdeny_check()
330 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);  in ivpu_boot_top_noc_qrenqn_check()
341 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);  in ivpu_boot_top_noc_qacceptn_check()
352 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);  in ivpu_boot_top_noc_qdeny_check()
363 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);  in ivpu_boot_idle_gen_drive()
401 	val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);  in ivpu_boot_host_ss_axi_drive()
438 	val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);  in ivpu_boot_host_ss_top_noc_drive()
468 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);  in ivpu_boot_pwr_island_trickle_drive()
483 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);  in ivpu_boot_pwr_island_drive()
507 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);  in ivpu_boot_pwr_island_isolation_drive()
519 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);  in ivpu_boot_no_snoop_enable()
530 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);  in ivpu_boot_tbu_mmu_enable()
544 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);  in ivpu_boot_cpu_noc_qacceptn_check()
554 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);  in ivpu_boot_cpu_noc_qdeny_check()
599 	val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);  in ivpu_boot_soc_cpu_drive()
640 	val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);  in ivpu_boot_soc_cpu_boot()
924 	val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);  in ivpu_hw_40xx_wdt_disable()
965 	return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);  in ivpu_hw_40xx_reg_ipc_rx_addr_get()
1021 	u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;  in ivpu_hw_40xx_irqv_handler()
1136 	u32 irqv = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;  in ivpu_hw_40xx_diagnose_failure()