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Searched refs:MDIO_MMD_VEND2 (Results 1 – 21 of 21) sorted by relevance

/Linux-v6.6/drivers/net/pcs/
Dpcs-xpcs-nxp.c74 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2, in nxp_sja1105_sgmii_pma_config()
89 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0, in nxp_sja1110_pma_config()
94 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1, in nxp_sja1110_pma_config()
100 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0, in nxp_sja1110_pma_config()
107 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val); in nxp_sja1110_pma_config()
113 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_1, val); in nxp_sja1110_pma_config()
122 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val); in nxp_sja1110_pma_config()
127 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0); in nxp_sja1110_pma_config()
134 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0, in nxp_sja1110_pma_config()
139 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1, in nxp_sja1110_pma_config()
[all …]
Dpcs-xpcs.c293 dev = MDIO_MMD_VEND2; in xpcs_soft_reset()
396 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); in xpcs_config_usxgmii()
403 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); in xpcs_config_usxgmii()
649 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); in xpcs_config_eee()
666 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); in xpcs_config_eee()
670 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); in xpcs_config_eee()
679 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); in xpcs_config_eee()
707 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); in xpcs_config_aneg_c37_sgmii()
712 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, in xpcs_config_aneg_c37_sgmii()
718 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); in xpcs_config_aneg_c37_sgmii()
[all …]
Dpcs-lynx.c45 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); in lynx_pcs_get_state_usxgmii()
54 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); in lynx_pcs_get_state_usxgmii()
165 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, in lynx_pcs_config_usxgmii()
/Linux-v6.6/drivers/net/ethernet/microchip/
Dlan743x_ethtool.c1238 { ETH_SR_MII_CTRL, MDIO_MMD_VEND2, 0x0000}, in lan743x_sgmii_regs()
1239 { ETH_SR_MII_STS, MDIO_MMD_VEND2, 0x0001}, in lan743x_sgmii_regs()
1240 { ETH_SR_MII_DEV_ID1, MDIO_MMD_VEND2, 0x0002}, in lan743x_sgmii_regs()
1241 { ETH_SR_MII_DEV_ID2, MDIO_MMD_VEND2, 0x0003}, in lan743x_sgmii_regs()
1242 { ETH_SR_MII_AN_ADV, MDIO_MMD_VEND2, 0x0004}, in lan743x_sgmii_regs()
1243 { ETH_SR_MII_LP_BABL, MDIO_MMD_VEND2, 0x0005}, in lan743x_sgmii_regs()
1244 { ETH_SR_MII_EXPN, MDIO_MMD_VEND2, 0x0006}, in lan743x_sgmii_regs()
1245 { ETH_SR_MII_EXT_STS, MDIO_MMD_VEND2, 0x000F}, in lan743x_sgmii_regs()
1246 { ETH_SR_MII_TIME_SYNC_ABL, MDIO_MMD_VEND2, 0x0708}, in lan743x_sgmii_regs()
1247 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x0709}, in lan743x_sgmii_regs()
[all …]
Dlan743x_main.c1001 mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1017 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1022 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1027 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1047 ret = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_is_sgmii_2_5G_mode()
1079 mii_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR); in lan743x_sgmii_aneg_update()
1083 an_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, VR_MII_AN_CTRL); in lan743x_sgmii_aneg_update()
1087 dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_aneg_update()
1103 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_aneg_update()
1114 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, in lan743x_sgmii_aneg_update()
[all …]
/Linux-v6.6/drivers/net/phy/
Dmicrochip_t1s.c99 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb0_indirect_read()
104 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb0_indirect_read()
109 return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA); in lan865x_revb0_indirect_read()
138 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in lan865x_read_cfg_params()
153 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_write_cfg_params()
204 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb0_config_init()
223 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_revb1_config_init()
229 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_revb1_config_init()
245 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revb1_config_init()
Ddp83td510.c61 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
67 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
73 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
78 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
93 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1); in dp83td510_handle_interrupt()
140 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_read_status()
183 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT); in dp83td510_get_sqi()
Dintel-xway.c255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init()
259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init()
277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
Dmarvell10g.c188 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); in mv3310_hwmon_read_temp_reg()
265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
272 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, in mv3310_hwmon_config()
319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_down()
328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
342 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
658 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); in mv3310_get_mactype()
670 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
676 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
1275 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); in mv3110_get_wol()
[all …]
Dphy-c45.c1201 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1210 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1216 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1223 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1229 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); in genphy_c45_plca_get_cfg()
1262 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1277 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1302 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1317 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
[all …]
Dmarvell-88x2222.c80 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
85 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
201 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
204 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
207 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
Dmxl-gpy.c681 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
688 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
695 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
708 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
722 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
758 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); in gpy_get_wol()
Dmediatek-ge-soc.c355 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, in rext_fill_result()
1131 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_hw_led_on_set()
1154 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_hw_led_blink_set()
1230 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mt798x_phy_led_hw_control_get()
1236 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mt798x_phy_led_hw_control_get()
1334 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_led_hw_control_set()
1347 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_led_hw_control_set()
1375 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt7988_phy_fix_leds_polarities()
Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
Dphy_device.c796 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
834 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
/Linux-v6.6/drivers/net/dsa/sja1105/
Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
23 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1105_pcs_mdio_read_c45()
25 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()
67 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1110_pcs_mdio_read_c45()
69 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1110_pcs_mdio_read_c45()
Dsja1105_main.c2317 MDIO_MMD_VEND2, MDIO_CTRL1); in sja1105_static_config_reload()
/Linux-v6.6/drivers/net/ethernet/amd/xgbe/
Dxgbe-mdio.c151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_clear_interrupts()
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_clear_interrupts()
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_disable_interrupts()
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_disable_interrupts()
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_enable_interrupts()
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_enable_interrupts()
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_isr()
670 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_isr()
[all …]
Dxgbe-phy-v2.c1659 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); in xgbe_phy_an37_outcome()
1660 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); in xgbe_phy_an37_outcome()
/Linux-v6.6/include/uapi/linux/
Dmdio.h28 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro
157 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
/Linux-v6.6/drivers/net/dsa/
Dmt7530.c163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); in core_write()
175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); in core_rmw()
178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); in core_rmw()
2516 MDIO_MMD_VEND2, CORE_PLL_GROUP4); in mt7531_setup()
2519 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, in mt7531_setup()