Lines Matching refs:MDIO_MMD_VEND2
1238 { ETH_SR_MII_CTRL, MDIO_MMD_VEND2, 0x0000}, in lan743x_sgmii_regs()
1239 { ETH_SR_MII_STS, MDIO_MMD_VEND2, 0x0001}, in lan743x_sgmii_regs()
1240 { ETH_SR_MII_DEV_ID1, MDIO_MMD_VEND2, 0x0002}, in lan743x_sgmii_regs()
1241 { ETH_SR_MII_DEV_ID2, MDIO_MMD_VEND2, 0x0003}, in lan743x_sgmii_regs()
1242 { ETH_SR_MII_AN_ADV, MDIO_MMD_VEND2, 0x0004}, in lan743x_sgmii_regs()
1243 { ETH_SR_MII_LP_BABL, MDIO_MMD_VEND2, 0x0005}, in lan743x_sgmii_regs()
1244 { ETH_SR_MII_EXPN, MDIO_MMD_VEND2, 0x0006}, in lan743x_sgmii_regs()
1245 { ETH_SR_MII_EXT_STS, MDIO_MMD_VEND2, 0x000F}, in lan743x_sgmii_regs()
1246 { ETH_SR_MII_TIME_SYNC_ABL, MDIO_MMD_VEND2, 0x0708}, in lan743x_sgmii_regs()
1247 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x0709}, in lan743x_sgmii_regs()
1248 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_UPR, MDIO_MMD_VEND2, 0x070A}, in lan743x_sgmii_regs()
1249 { ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_LWR, MDIO_MMD_VEND2, 0x070B}, in lan743x_sgmii_regs()
1250 { ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_UPR, MDIO_MMD_VEND2, 0x070C}, in lan743x_sgmii_regs()
1251 { ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x070D}, in lan743x_sgmii_regs()
1252 { ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_UPR, MDIO_MMD_VEND2, 0x070E}, in lan743x_sgmii_regs()
1253 { ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_LWR, MDIO_MMD_VEND2, 0x070F}, in lan743x_sgmii_regs()
1254 { ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_UPR, MDIO_MMD_VEND2, 0x0710}, in lan743x_sgmii_regs()
1255 { ETH_VR_MII_DIG_CTRL1, MDIO_MMD_VEND2, 0x8000}, in lan743x_sgmii_regs()
1256 { ETH_VR_MII_AN_CTRL, MDIO_MMD_VEND2, 0x8001}, in lan743x_sgmii_regs()
1257 { ETH_VR_MII_AN_INTR_STS, MDIO_MMD_VEND2, 0x8002}, in lan743x_sgmii_regs()
1258 { ETH_VR_MII_TC, MDIO_MMD_VEND2, 0x8003}, in lan743x_sgmii_regs()
1259 { ETH_VR_MII_DBG_CTRL, MDIO_MMD_VEND2, 0x8005}, in lan743x_sgmii_regs()
1260 { ETH_VR_MII_EEE_MCTRL0, MDIO_MMD_VEND2, 0x8006}, in lan743x_sgmii_regs()
1261 { ETH_VR_MII_EEE_TXTIMER, MDIO_MMD_VEND2, 0x8008}, in lan743x_sgmii_regs()
1262 { ETH_VR_MII_EEE_RXTIMER, MDIO_MMD_VEND2, 0x8009}, in lan743x_sgmii_regs()
1263 { ETH_VR_MII_LINK_TIMER_CTRL, MDIO_MMD_VEND2, 0x800A}, in lan743x_sgmii_regs()
1264 { ETH_VR_MII_EEE_MCTRL1, MDIO_MMD_VEND2, 0x800B}, in lan743x_sgmii_regs()
1265 { ETH_VR_MII_DIG_STS, MDIO_MMD_VEND2, 0x8010}, in lan743x_sgmii_regs()
1266 { ETH_VR_MII_ICG_ERRCNT1, MDIO_MMD_VEND2, 0x8011}, in lan743x_sgmii_regs()
1267 { ETH_VR_MII_GPIO, MDIO_MMD_VEND2, 0x8015}, in lan743x_sgmii_regs()
1268 { ETH_VR_MII_EEE_LPI_STATUS, MDIO_MMD_VEND2, 0x8016}, in lan743x_sgmii_regs()
1269 { ETH_VR_MII_EEE_WKERR, MDIO_MMD_VEND2, 0x8017}, in lan743x_sgmii_regs()
1270 { ETH_VR_MII_MISC_STS, MDIO_MMD_VEND2, 0x8018}, in lan743x_sgmii_regs()
1271 { ETH_VR_MII_RX_LSTS, MDIO_MMD_VEND2, 0x8020}, in lan743x_sgmii_regs()
1272 { ETH_VR_MII_GEN2_GEN4_TX_BSTCTRL0, MDIO_MMD_VEND2, 0x8038}, in lan743x_sgmii_regs()
1273 { ETH_VR_MII_GEN2_GEN4_TX_LVLCTRL0, MDIO_MMD_VEND2, 0x803A}, in lan743x_sgmii_regs()
1274 { ETH_VR_MII_GEN2_GEN4_TXGENCTRL0, MDIO_MMD_VEND2, 0x803C}, in lan743x_sgmii_regs()
1275 { ETH_VR_MII_GEN2_GEN4_TXGENCTRL1, MDIO_MMD_VEND2, 0x803D}, in lan743x_sgmii_regs()
1276 { ETH_VR_MII_GEN4_TXGENCTRL2, MDIO_MMD_VEND2, 0x803E}, in lan743x_sgmii_regs()
1277 { ETH_VR_MII_GEN2_GEN4_TX_STS, MDIO_MMD_VEND2, 0x8048}, in lan743x_sgmii_regs()
1278 { ETH_VR_MII_GEN2_GEN4_RXGENCTRL0, MDIO_MMD_VEND2, 0x8058}, in lan743x_sgmii_regs()
1279 { ETH_VR_MII_GEN2_GEN4_RXGENCTRL1, MDIO_MMD_VEND2, 0x8059}, in lan743x_sgmii_regs()
1280 { ETH_VR_MII_GEN4_RXEQ_CTRL, MDIO_MMD_VEND2, 0x805B}, in lan743x_sgmii_regs()
1281 { ETH_VR_MII_GEN4_RXLOS_CTRL0, MDIO_MMD_VEND2, 0x805D}, in lan743x_sgmii_regs()
1282 { ETH_VR_MII_GEN2_GEN4_MPLL_CTRL0, MDIO_MMD_VEND2, 0x8078}, in lan743x_sgmii_regs()
1283 { ETH_VR_MII_GEN2_GEN4_MPLL_CTRL1, MDIO_MMD_VEND2, 0x8079}, in lan743x_sgmii_regs()
1284 { ETH_VR_MII_GEN2_GEN4_MPLL_STS, MDIO_MMD_VEND2, 0x8088}, in lan743x_sgmii_regs()
1285 { ETH_VR_MII_GEN2_GEN4_LVL_CTRL, MDIO_MMD_VEND2, 0x8090}, in lan743x_sgmii_regs()
1286 { ETH_VR_MII_GEN4_MISC_CTRL2, MDIO_MMD_VEND2, 0x8093}, in lan743x_sgmii_regs()
1287 { ETH_VR_MII_GEN2_GEN4_MISC_CTRL0, MDIO_MMD_VEND2, 0x8099}, in lan743x_sgmii_regs()
1288 { ETH_VR_MII_GEN2_GEN4_MISC_CTRL1, MDIO_MMD_VEND2, 0x809A}, in lan743x_sgmii_regs()
1289 { ETH_VR_MII_SNPS_CR_CTRL, MDIO_MMD_VEND2, 0x80A0}, in lan743x_sgmii_regs()
1290 { ETH_VR_MII_SNPS_CR_ADDR, MDIO_MMD_VEND2, 0x80A1}, in lan743x_sgmii_regs()
1291 { ETH_VR_MII_SNPS_CR_DATA, MDIO_MMD_VEND2, 0x80A2}, in lan743x_sgmii_regs()
1292 { ETH_VR_MII_DIG_CTRL2, MDIO_MMD_VEND2, 0x80E1}, in lan743x_sgmii_regs()
1293 { ETH_VR_MII_DIG_ERRCNT, MDIO_MMD_VEND2, 0x80E2}, in lan743x_sgmii_regs()