Searched refs:IS_DG2 (Results 1 – 25 of 33) sorted by relevance
12
938 else if (IS_DG2(i915)) in __intel_engine_init_ctx_wa()1392 if (IS_DG2(gt->i915)) in xehp_init_mcr()1807 if (IS_DG2(gt->i915)) { in gt_tuning_settings()1833 else if (IS_DG2(i915)) in gt_init_workarounds()2323 else if (IS_DG2(i915)) in intel_engine_init_whitelist()2532 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()2981 if (IS_METEORLAKE(i915) || IS_DG2(i915)) in add_render_compute_tuning_settings()3063 IS_DG2(i915)) { in general_render_compute_wa_init()3070 IS_DG2(i915)) { in general_render_compute_wa_init()3118 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { in general_render_compute_wa_init()[all …]
190 } else if (IS_DG2(i915)) { in intel_gt_mcr_init()637 *group = IS_DG2(gt->i915) ? 1 : 0; in get_nonterminated_steering()
192 } else if (IS_DG2(i915)) { in gsc_init_one()
523 } else if (IS_DG2(i915)) { in get_mocs_settings()
648 if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES) in gen8_reset_engines()
1381 IS_DG2(ce->engine->i915)) in gen12_emit_indirect_ctx_rcs()
308 if (IS_DG2(i915)) { in intel_huc_init_early()356 if (IS_DG2(gt->i915)) { in check_huc_loading_mode()
281 IS_DG2(gt->i915)) in guc_ctl_wa_flags()291 if (IS_DG2(gt->i915)) in guc_ctl_wa_flags()
289 if (IS_DG1(i915) || IS_DG2(i915)) in hwm_pcode_read_i1()309 return IS_DG1(i915) || IS_DG2(i915) ? 0444 : 0; in hwm_in_is_visible()735 if (IS_DG1(i915) || IS_DG2(i915)) { in hwm_get_preregistration_info()
572 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) macro693 (IS_DG2(__i915) && \
850 else if (IS_DG2(i915)) in intel_clock_gating_hooks_init()
2892 if (IS_XEHPSDV(i915) || IS_DG2(i915)) { in gen12_enable_metric_set()2981 if (IS_XEHPSDV(i915) || IS_DG2(i915)) { in gen12_disable_metric_set()3233 if (IS_DG2(i915) || IS_METEORLAKE(i915)) { in i915_perf_oa_timestamp_frequency()
1495 if (IS_DG2(dev_priv)) in bxt_de_pll_readout()1843 return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) && in pll_enable_wa_needed()1912 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()1948 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) in bxt_set_cdclk()2268 if (!IS_DG2(i915)) in intel_pcode_notify()2462 if (IS_DG2(i915)) in intel_set_cdclk_pre_plane_update()2494 if (IS_DG2(i915)) in intel_set_cdclk_post_plane_update()2631 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()3026 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); in intel_cdclk_need_serialize()3565 } else if (IS_DG2(dev_priv)) { in intel_init_cdclk_hooks()
45 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
375 if (IS_DG2(i915)) { in get_flip_queue_event_regs()392 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) in disable_all_flip_queue_events()1004 } else if (IS_DG2(i915)) { in intel_dmc_init()
950 if (IS_DG2(dev_priv)) in get_allowed_dc_mask()1696 if (IS_DG2(dev_priv)) in icl_display_core_init()
668 else if (IS_DG2(dev_priv)) in intel_bw_init_hw()
1714 } else if (IS_DG2(i915)) { in intel_ddi_buf_trans_init()
1657 else if (IS_DG2(i915)) in intel_display_power_map_init()
818 if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915)) in intel_fbc_program_workarounds()
216 } else if (IS_DG2(dev_priv)) { in intel_wait_ddi_buf_active()4863 } else if (IS_DG2(dev_priv)) { in intel_ddi_init()4925 } else if (IS_DG2(dev_priv)) { in intel_ddi_init()
265 if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) { in hsw_wait_for_power_well_enable()
2004 if (!IS_DG2(i915)) in intel_mpllb_state_verify()
225 } else if (IS_DG2(dev_priv)) { in intel_detect_pch()
662 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) in intel_dram_detect()
