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Searched refs:DISPLAY_VER (Results 1 – 25 of 75) sorted by relevance

123

/Linux-v6.6/drivers/gpu/drm/i915/display/
Dintel_display_device.h35 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
38 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
43 #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
45 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
46 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
51 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
52 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
53 #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
55 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
59 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
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Di9xx_plane.c120 else if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_has_fbc()
142 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_plane_has_windowing()
144 else if (DISPLAY_VER(dev_priv) == 4) in i9xx_plane_has_windowing()
211 if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_plane_ctl()
250 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_check_plane_surface()
267 if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { in i9xx_check_plane_surface()
306 } else if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_check_plane_surface()
364 if (DISPLAY_VER(dev_priv) < 5) in i9xx_plane_ctl_crtc()
427 if (DISPLAY_VER(dev_priv) < 4) { in i9xx_plane_update_noarm()
459 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_update_arm()
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Dintel_fbc.c162 if (DISPLAY_VER(i915) >= 11) in skl_fbc_min_cfb_stride()
186 if (DISPLAY_VER(i915) >= 9) in intel_fbc_cfb_stride()
197 if (DISPLAY_VER(i915) == 7) in intel_fbc_cfb_size()
199 else if (DISPLAY_VER(i915) >= 8) in intel_fbc_cfb_size()
220 (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) in intel_fbc_override_cfb_stride()
236 if (DISPLAY_VER(i915) == 2) in i8xx_fbc_ctl()
299 if (DISPLAY_VER(i915) == 4) { in i8xx_fbc_activate()
405 if (DISPLAY_VER(i915) < 6) in g4x_dpfc_ctl()
606 if (DISPLAY_VER(i915) >= 10) in ivb_fbc_activate()
608 else if (DISPLAY_VER(i915) == 9) in ivb_fbc_activate()
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Dintel_wm.c165 if (DISPLAY_VER(dev_priv) >= 9) in intel_print_wm_latency()
178 if (DISPLAY_VER(i915) >= 9) in intel_wm_init()
198 if (DISPLAY_VER(dev_priv) >= 9 || in wm_latency_show()
218 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_show()
233 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_show()
248 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_show()
262 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in pri_wm_latency_open()
329 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_write()
344 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_write()
359 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_write()
Dintel_display_irq.c187 if (DISPLAY_VER(dev_priv) < 5) in i915_pipestat_enable_mask()
289 if (DISPLAY_VER(dev_priv) >= 4) in i915_enable_asle_pipestat()
319 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { in display_pipe_crc_irq_handler()
381 if (DISPLAY_VER(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
386 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
737 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT) in ilk_display_irq_handler()
795 if (DISPLAY_VER(dev_priv) >= 14) in gen8_de_port_aux_mask()
798 else if (DISPLAY_VER(dev_priv) >= 13) in gen8_de_port_aux_mask()
808 else if (DISPLAY_VER(dev_priv) >= 12) in gen8_de_port_aux_mask()
820 if (DISPLAY_VER(dev_priv) >= 9) in gen8_de_port_aux_mask()
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Dskl_universal_plane.c237 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) in icl_nv12_y_plane_mask()
246 return DISPLAY_VER(dev_priv) >= 11 && in icl_is_nv12_y_plane()
257 return DISPLAY_VER(dev_priv) >= 11 && in icl_is_hdr_plane()
472 if (DISPLAY_VER(i915) >= 13) { in skl_plane_max_stride()
885 if (DISPLAY_VER(dev_priv) >= 10) in skl_plane_ctl_crtc()
909 if (DISPLAY_VER(dev_priv) < 10) { in skl_plane_ctl()
924 if (DISPLAY_VER(dev_priv) >= 11) in skl_plane_ctl()
934 if (DISPLAY_VER(dev_priv) == 13) in skl_plane_ctl()
945 if (DISPLAY_VER(dev_priv) >= 11) in glk_plane_color_ctl_crtc()
1045 if (DISPLAY_VER(i915) < 12) in skl_plane_aux_dist()
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Dintel_psr.c209 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
217 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : in psr_irq_post_exit_bit_get()
225 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : in psr_irq_pre_entry_bit_get()
233 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : in psr_irq_mask_get()
240 if (DISPLAY_VER(dev_priv) >= 8) in psr_ctl_reg()
249 if (DISPLAY_VER(dev_priv) >= 8) in psr_debug_reg()
258 if (DISPLAY_VER(dev_priv) >= 8) in psr_perf_cnt_reg()
267 if (DISPLAY_VER(dev_priv) >= 8) in psr_status_reg()
276 if (DISPLAY_VER(dev_priv) >= 12) in psr_imr_reg()
285 if (DISPLAY_VER(dev_priv) >= 12) in psr_iir_reg()
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Dintel_bw.c90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000); in icl_pcode_read_qgv_point_info()
153 if (DISPLAY_VER(dev_priv) >= 14) in icl_pcode_restrict_qgv_points()
202 if (DISPLAY_VER(dev_priv) >= 14) in intel_read_qgv_point_info()
220 if (DISPLAY_VER(dev_priv) >= 14) { in icl_get_qgv_points()
245 } else if (DISPLAY_VER(dev_priv) >= 12) { in icl_get_qgv_points()
279 } else if (DISPLAY_VER(dev_priv) == 11) { in icl_get_qgv_points()
474 if (DISPLAY_VER(dev_priv) < 14 && in tgl_get_bw_info()
480 if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12) in tgl_get_bw_info()
483 if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels) in tgl_get_bw_info()
666 if (DISPLAY_VER(dev_priv) >= 14) in intel_bw_init_hw()
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Dintel_fifo_underrun.c196 if (DISPLAY_VER(dev_priv) >= 13) in icl_pipe_status_underrun_mask()
211 if (DISPLAY_VER(dev_priv) >= 11) in bdw_set_fifo_underrun_reporting()
297 else if (DISPLAY_VER(dev_priv) == 7) in __intel_set_cpu_fifo_underrun_reporting()
299 else if (DISPLAY_VER(dev_priv) >= 8) in __intel_set_cpu_fifo_underrun_reporting()
420 if (DISPLAY_VER(dev_priv) >= 11) { in intel_cpu_fifo_underrun_irq_handler()
429 if (DISPLAY_VER(dev_priv) >= 11) in intel_cpu_fifo_underrun_irq_handler()
484 else if (DISPLAY_VER(dev_priv) == 7) in intel_check_cpu_fifo_underruns()
Dintel_ddi.c105 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); in has_buf_trans_select()
110 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); in has_iboost()
209 if (DISPLAY_VER(dev_priv) < 10) { in intel_wait_ddi_buf_active()
214 if (DISPLAY_VER(dev_priv) >= 14) { in intel_wait_ddi_buf_active()
218 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_wait_ddi_buf_active()
227 if (DISPLAY_VER(dev_priv) >= 14) in intel_wait_ddi_buf_active()
337 if (DISPLAY_VER(i915) >= 14) { in intel_ddi_init_dp_buf_reg()
484 if (DISPLAY_VER(dev_priv) >= 12) in intel_ddi_transcoder_func_reg_val_get()
546 if (DISPLAY_VER(dev_priv) >= 14) in intel_ddi_transcoder_func_reg_val_get()
558 if (DISPLAY_VER(dev_priv) >= 12) { in intel_ddi_transcoder_func_reg_val_get()
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Dintel_sprite_uapi.c13 return DISPLAY_VER(dev_priv) >= 9; in has_dst_key_in_primary_plane()
37 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && in intel_plane_set_ckey()
76 if (DISPLAY_VER(dev_priv) >= 9 && in intel_sprite_set_colorkey_ioctl()
Dintel_crtc.c114 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in intel_crtc_max_vblank_count()
116 else if (DISPLAY_VER(dev_priv) >= 3) in intel_crtc_max_vblank_count()
311 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
327 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
350 else if (DISPLAY_VER(dev_priv) == 4) in intel_crtc_init()
354 else if (DISPLAY_VER(dev_priv) == 3) in intel_crtc_init()
359 if (DISPLAY_VER(dev_priv) >= 8) in intel_crtc_init()
371 if (DISPLAY_VER(dev_priv) >= 11) in intel_crtc_init()
660 if (DISPLAY_VER(dev_priv) >= 11 && in intel_pipe_update_end()
Dintel_display_power.c954 else if (DISPLAY_VER(dev_priv) >= 12) in get_allowed_dc_mask()
958 else if (DISPLAY_VER(dev_priv) >= 9) in get_allowed_dc_mask()
969 DISPLAY_VER(dev_priv) >= 11 ? in get_allowed_dc_mask()
1117 if (DISPLAY_VER(dev_priv) >= 14) in gen9_dbuf_enable()
1131 if (DISPLAY_VER(dev_priv) >= 14) in gen9_dbuf_disable()
1153 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in icl_mbus_init()
1170 if (DISPLAY_VER(dev_priv) == 12) in icl_mbus_init()
1430 if (DISPLAY_VER(dev_priv) >= 14) in intel_pch_reset_handshake()
1635 if (DISPLAY_VER(dev_priv) == 12) in tgl_bw_buddy_init()
1675 if (DISPLAY_VER(dev_priv) == 14) in icl_display_core_init()
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Dintel_vrr.c81 if (DISPLAY_VER(i915) >= 13) in intel_vrr_vblank_exit_length()
142 if (DISPLAY_VER(i915) >= 13) { in intel_vrr_compute_config()
161 if (DISPLAY_VER(i915) >= 13) in trans_vrr_ctl()
179 if (DISPLAY_VER(dev_priv) == 13) in intel_vrr_set_transcoder_timings()
258 if (DISPLAY_VER(dev_priv) >= 13) in intel_vrr_get_config()
Dskl_watermark.c63 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
76 if (DISPLAY_VER(i915) >= 14) { in intel_sagv_block_time()
82 } else if (DISPLAY_VER(i915) >= 12) { in intel_sagv_block_time()
95 } else if (DISPLAY_VER(i915) == 11) { in intel_sagv_block_time()
113 if (DISPLAY_VER(i915) < 11) in intel_sagv_init()
312 if (DISPLAY_VER(i915) >= 11) in intel_sagv_pre_plane_update()
332 if (DISPLAY_VER(i915) >= 11) in intel_sagv_post_plane_update()
418 if (DISPLAY_VER(i915) >= 12) in intel_crtc_can_enable_sagv()
427 if (DISPLAY_VER(i915) < 11 && in intel_can_enable_sagv()
492 DISPLAY_VER(i915) >= 12 && in intel_compute_sagv_mask()
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Dintel_display.c291 if (DISPLAY_VER(dev_priv) >= 4) { in intel_wait_for_pipe_off()
427 if (DISPLAY_VER(dev_priv) == 13) in intel_enable_transcoder()
486 if (DISPLAY_VER(dev_priv) >= 14) in intel_disable_transcoder()
489 else if (DISPLAY_VER(dev_priv) >= 12) in intel_disable_transcoder()
539 return DISPLAY_VER(dev_priv) < 4 || in intel_plane_uses_fence()
678 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic()
725 else if (DISPLAY_VER(dev_priv) >= 13) in icl_set_pipe_chicken()
840 if (DISPLAY_VER(dev_priv) == 9) in needs_nv12_wa()
851 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) in needs_scalerclk_wa()
864 DISPLAY_VER(dev_priv) == 11) in needs_cursorclk_wa()
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Dskl_scaler.c133 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable && in skl_update_scaler()
177 if (DISPLAY_VER(dev_priv) < 11) { in skl_update_scaler()
182 } else if (DISPLAY_VER(dev_priv) < 12) { in skl_update_scaler()
187 } else if (DISPLAY_VER(dev_priv) < 14) { in skl_update_scaler()
337 if (DISPLAY_VER(dev_priv) >= 11) in skl_update_scaler_plane()
383 if (DISPLAY_VER(dev_priv) == 9) { in intel_atomic_setup_scaler()
401 } else if (DISPLAY_VER(dev_priv) >= 10) { in intel_atomic_setup_scaler()
435 if (DISPLAY_VER(dev_priv) >= 14) { in intel_atomic_setup_scaler()
448 } else if (DISPLAY_VER(dev_priv) >= 10 || in intel_atomic_setup_scaler()
572 if (DISPLAY_VER(dev_priv) >= 10) in intel_atomic_setup_scalers()
Dintel_dp_mst.c53 if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) { in intel_dp_mst_check_constraints()
198 if (DISPLAY_VER(i915) >= 12) in intel_dp_dsc_mst_compute_link_config()
410 if (DISPLAY_VER(dev_priv) < 12) in intel_dp_mst_transcoder_mask()
462 if (DISPLAY_VER(dev_priv) < 12) in intel_dp_mst_atomic_master_trans_check()
597 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && in intel_mst_post_disable_dp()
613 if (DISPLAY_VER(dev_priv) >= 9) in intel_mst_post_disable_dp()
639 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) in intel_mst_post_disable_dp()
710 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && in intel_mst_pre_enable_dp()
740 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) in intel_mst_pre_enable_dp()
788 if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable) in intel_mst_enable_dp()
[all …]
Dintel_dp_aux.c204 if (DISPLAY_VER(i915) >= 14) in skl_get_aux_send_ctl()
732 if (DISPLAY_VER(dev_priv) >= 14) { in intel_dp_aux_init()
735 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_dp_aux_init()
738 } else if (DISPLAY_VER(dev_priv) >= 9) { in intel_dp_aux_init()
749 if (DISPLAY_VER(dev_priv) >= 9) in intel_dp_aux_init()
758 if (DISPLAY_VER(dev_priv) >= 9) in intel_dp_aux_init()
767 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) in intel_dp_aux_init()
771 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) in intel_dp_aux_init()
789 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) in default_aux_ch()
Dintel_dmc.c368 if (DISPLAY_VER(i915) == 12) { in get_flip_queue_event_regs()
414 if (DISPLAY_VER(i915) < 12) in disable_all_event_handlers()
464 if (DISPLAY_VER(i915) >= 14 && enable) in pipedmc_clock_gating_wa()
466 else if (DISPLAY_VER(i915) == 13) in pipedmc_clock_gating_wa()
477 if (DISPLAY_VER(i915) >= 14) in intel_dmc_enable_pipe()
490 if (DISPLAY_VER(i915) >= 14) in intel_dmc_disable_pipe()
651 } else if (DISPLAY_VER(i915) >= 13) { in dmc_mmio_addr_sanity_check()
654 } else if (DISPLAY_VER(i915) >= 12) { in dmc_mmio_addr_sanity_check()
1022 } else if (DISPLAY_VER(i915) == 11) { in intel_dmc_init()
1177 DISPLAY_VER(i915) >= 14)); in intel_dmc_debugfs_status_show()
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Dintel_cdclk.c1497 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1517 if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1534 if (DISPLAY_VER(dev_priv) >= 12) in bxt_get_cdclk()
1536 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_get_cdclk()
1676 if (DISPLAY_VER(dev_priv) >= 12) { in bxt_cdclk_cd2x_pipe()
1681 } else if (DISPLAY_VER(dev_priv) >= 11) { in bxt_cdclk_cd2x_pipe()
1862 } else if (DISPLAY_VER(dev_priv) >= 11) { in _bxt_set_cdclk()
1912 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()
1914 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
1943 if (DISPLAY_VER(dev_priv) >= 14) in bxt_set_cdclk()
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Dintel_pipe_crc.c405 if (DISPLAY_VER(dev_priv) == 2) in get_new_crc_ctl_reg()
407 else if (DISPLAY_VER(dev_priv) < 5) in get_new_crc_ctl_reg()
413 else if (DISPLAY_VER(dev_priv) < 9) in get_new_crc_ctl_reg()
535 if (DISPLAY_VER(dev_priv) == 2) in intel_is_valid_crc_source()
537 else if (DISPLAY_VER(dev_priv) < 5) in intel_is_valid_crc_source()
543 else if (DISPLAY_VER(dev_priv) < 9) in intel_is_valid_crc_source()
Dintel_pmdemand.c116 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_update_phys_mask()
137 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_update_port_clock()
314 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_atomic_check()
389 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_init_pmdemand_params()
585 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_pre_plane_update()
608 if (DISPLAY_VER(i915) < 14) in intel_pmdemand_post_plane_update()
Dintel_display_device.c892 else if (DISPLAY_VER(i915) >= 11) { in intel_display_device_info_runtime_init()
895 } else if (DISPLAY_VER(i915) >= 9) { in intel_display_device_info_runtime_init()
901 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) in intel_display_device_info_runtime_init()
904 else if (DISPLAY_VER(i915) >= 11) in intel_display_device_info_runtime_init()
907 else if (DISPLAY_VER(i915) == 10) in intel_display_device_info_runtime_init()
926 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { in intel_display_device_info_runtime_init()
931 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && in intel_display_device_info_runtime_init()
962 } else if (DISPLAY_VER(i915) >= 9) { in intel_display_device_info_runtime_init()
979 if (DISPLAY_VER(i915) >= 12 && in intel_display_device_info_runtime_init()
994 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) in intel_display_device_info_runtime_init()
Dintel_fb.c603 else if (DISPLAY_VER(i915) < 11 && in skl_main_to_aux_plane()
612 return DISPLAY_VER(i915) == 2 ? 2048 : 4096; in intel_tile_size()
625 if (DISPLAY_VER(dev_priv) == 2) in intel_tile_width_bytes()
653 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv)) in intel_tile_width_bytes()
781 if (DISPLAY_VER(dev_priv) >= 9) in intel_linear_alignment()
786 else if (DISPLAY_VER(dev_priv) >= 4) in intel_linear_alignment()
809 if (DISPLAY_VER(dev_priv) >= 12) { in intel_surf_alignment()
1100 if (DISPLAY_VER(i915) >= 12 && in intel_fb_offset_to_xy()
1206 if (DISPLAY_VER(i915) < 4) in intel_plane_can_remap()
1233 return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && in intel_fb_needs_pot_stride_remap()
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