Searched refs:CLK_TOP_APLL2_DIV0 (Results 1 – 5 of 5) sorted by relevance
| /Linux-v6.6/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 132 #define CLK_TOP_APLL2_DIV0 121 macro
|
| D | mt8173-clk.h | 137 #define CLK_TOP_APLL2_DIV0 127 macro
|
| /Linux-v6.6/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 518 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
|
| D | clk-mt8173-topckgen.c | 613 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
|
| /Linux-v6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 861 <&topckgen CLK_TOP_APLL2_DIV0>,
|
