Searched refs:wcreg (Results 1 – 2 of 2) sorted by relevance
184 u32 wcreg; /* cached write control register value */ member222 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)407 writel(rme32->wcreg | RME32_WCR_PD, in snd_rme32_reset_dac()409 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); in snd_rme32_reset_dac()416 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + in snd_rme32_playback_getrate()417 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); in snd_rme32_playback_getrate()431 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; in snd_rme32_playback_getrate()499 ds = rme32->wcreg & RME32_WCR_DS_BM; in snd_rme32_playback_setrate()502 rme32->wcreg &= ~RME32_WCR_DS_BM; in snd_rme32_playback_setrate()503 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & in snd_rme32_playback_setrate()[all …]
214 u32 wcreg; /* cached write control register value */ member256 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)257 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)535 writel(rme96->wcreg | RME96_WCR_PD, in snd_rme96_reset_dac()537 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); in snd_rme96_reset_dac()543 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + in snd_rme96_getmontracks()544 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); in snd_rme96_getmontracks()552 rme96->wcreg |= RME96_WCR_MONITOR_0; in snd_rme96_setmontracks()554 rme96->wcreg &= ~RME96_WCR_MONITOR_0; in snd_rme96_setmontracks()557 rme96->wcreg |= RME96_WCR_MONITOR_1; in snd_rme96_setmontracks()[all …]
