214 	u32 wcreg;    /* cached write control register value */  member
256 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
257 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
535 	writel(rme96->wcreg | RME96_WCR_PD,  in snd_rme96_reset_dac()
537 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_reset_dac()
543 	return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +  in snd_rme96_getmontracks()
544 		(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);  in snd_rme96_getmontracks()
552 		rme96->wcreg |= RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
554 		rme96->wcreg &= ~RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
557 		rme96->wcreg |= RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
559 		rme96->wcreg &= ~RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
561 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setmontracks()
568 	return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +  in snd_rme96_getattenuation()
569 		(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);  in snd_rme96_getattenuation()
578 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
582 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
586 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
590 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
596 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setattenuation()
668 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_getrate()
677 	rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +  in snd_rme96_playback_getrate()
678 		(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);  in snd_rme96_playback_getrate()
692 	return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;  in snd_rme96_playback_getrate()
701 	ds = rme96->wcreg & RME96_WCR_DS;  in snd_rme96_playback_setrate()
704 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
705 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
709 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
710 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
714 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
715 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
719 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
720 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
724 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
725 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
729 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
730 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
736 	if ((!ds && rme96->wcreg & RME96_WCR_DS) ||  in snd_rme96_playback_setrate()
737 	    (ds && !(rme96->wcreg & RME96_WCR_DS)))  in snd_rme96_playback_setrate()
743 		writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setrate()
797 		rme96->wcreg &= ~RME96_WCR_MASTER;  in snd_rme96_setclockmode()
802 		rme96->wcreg |= RME96_WCR_MASTER;  in snd_rme96_setclockmode()
807 		rme96->wcreg |= RME96_WCR_MASTER;   in snd_rme96_setclockmode()
813 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setclockmode()
824 	return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :  in snd_rme96_getclockmode()
836 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
840 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
844 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
856 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
885 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setinputtype()
895 	return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +  in snd_rme96_getinputtype()
896 		(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);  in snd_rme96_getinputtype()
913 		frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;  in snd_rme96_setframelog()
916 		frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;  in snd_rme96_setframelog()
926 		rme96->wcreg &= ~RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
929 		rme96->wcreg |= RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
934 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setformat()
943 		rme96->wcreg &= ~RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
946 		rme96->wcreg |= RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
951 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_capture_setformat()
961 		rme96->wcreg &= ~RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
964 		rme96->wcreg |= RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
970 	rme96->wcreg &= ~RME96_WCR_IDIS;  in snd_rme96_set_period_properties()
971 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_set_period_properties()
990 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_hw_params()
1022 	if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {  in snd_rme96_playback_hw_params()
1023 		rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_playback_hw_params()
1024 		writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_hw_params()
1113 		rme96->wcreg |= RME96_WCR_START;  in snd_rme96_trigger()
1115 		rme96->wcreg &= ~RME96_WCR_START;  in snd_rme96_trigger()
1117 		rme96->wcreg |= RME96_WCR_START_2;  in snd_rme96_trigger()
1119 		rme96->wcreg &= ~RME96_WCR_START_2;  in snd_rme96_trigger()
1120 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_trigger()
1194 	rme96->wcreg &= ~RME96_WCR_ADAT;  in snd_rme96_playback_spdif_open()
1195 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_spdif_open()
1200 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_spdif_open()
1264 	rme96->wcreg |= RME96_WCR_ADAT;  in snd_rme96_playback_adat_open()
1265 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_adat_open()
1270 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_adat_open()
1333 	spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;  in snd_rme96_playback_close()
1668 	rme96->wcreg =  in snd_rme96_create()
1676 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_create()
1726 	if (rme96->wcreg & RME96_WCR_IDIS) {  in snd_rme96_proc_read()
1729 	} else if (rme96->wcreg & RME96_WCR_ISEL) {  in snd_rme96_proc_read()
1763 	if (rme96->wcreg & RME96_WCR_MODE24_2) {  in snd_rme96_proc_read()
1770 	if (rme96->wcreg & RME96_WCR_SEL) {  in snd_rme96_proc_read()
1777 	if (rme96->wcreg & RME96_WCR_MODE24) {  in snd_rme96_proc_read()
1784 	} else if (rme96->wcreg & RME96_WCR_MASTER) {  in snd_rme96_proc_read()
1793 	if (rme96->wcreg & RME96_WCR_PRO) {  in snd_rme96_proc_read()
1798 	if (rme96->wcreg & RME96_WCR_EMP) {  in snd_rme96_proc_read()
1803 	if (rme96->wcreg & RME96_WCR_DOLBY) {  in snd_rme96_proc_read()
1860 	ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;  in snd_rme96_get_loopback_control()
1873 	val = (rme96->wcreg & ~RME96_WCR_SEL) | val;  in snd_rme96_put_loopback_control()
1874 	change = val != rme96->wcreg;  in snd_rme96_put_loopback_control()
1875 	rme96->wcreg = val;  in snd_rme96_put_loopback_control()
2173 	rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_control_spdif_stream_put()
2174 	rme96->wcreg |= val;  in snd_rme96_control_spdif_stream_put()
2175 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_control_spdif_stream_put()