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Searched refs:tdc2dev (Results 1 – 3 of 3) sorted by relevance

/Linux-v6.1/drivers/dma/
Dtegra20-apb-dma.c263 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) in tdc2dev() function
341 dev_err(tdc2dev(tdc), "Configuration not allowed\n"); in tegra_dma_slave_config()
427 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); in tegra_dma_stop()
475 dev_err(tdc2dev(tdc), in tegra_dma_configure_for_next()
564 dev_err(tdc2dev(tdc), "DMA transfer underflow, aborting DMA\n"); in handle_continuous_head_request()
686 dev_info(tdc2dev(tdc), "Interrupt already served status 0x%08x\n", in tegra_dma_isr()
716 dev_err(tdc2dev(tdc), "No DMA request\n"); in tegra_dma_issue_pending()
722 dev_err(tdc2dev(tdc), "Failed to enable DMA\n"); in tegra_dma_issue_pending()
761 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__); in tegra_dma_terminate_all()
817 dev_err(tdc2dev(tdc), "Failed to synchronize DMA: %d\n", err); in tegra_dma_synchronize()
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Dtegra186-gpc-dma.c277 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) in tdc2dev() function
284 dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", in tegra_dma_dump_chan_regs()
286 dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n", in tegra_dma_dump_chan_regs()
293 dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n", in tegra_dma_dump_chan_regs()
300 dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n", in tegra_dma_dump_chan_regs()
388 dev_err(tdc2dev(tdc), "DMA pause timed out\n"); in tegra_dma_pause()
462 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); in tegra_dma_disable()
687 dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n"); in tegra_dma_stop_client()
774 dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie); in tegra_dma_tx_status()
792 dev_err(tdc2dev(tdc), "given slave bus width is not supported\n"); in get_bus_width()
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Dtegra210-adma.c198 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc) in tdc2dev() function
340 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n"); in tegra_adma_stop()
362 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n"); in tegra_adma_start()
464 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n"); in tegra_adma_pause()
589 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); in tegra_adma_set_xfer_params()
635 dev_err(tdc2dev(tdc), "invalid buffer/period len\n"); in tegra_adma_prep_dma_cyclic()
640 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n"); in tegra_adma_prep_dma_cyclic()
645 dev_err(tdc2dev(tdc), "invalid buffer alignment\n"); in tegra_adma_prep_dma_cyclic()
672 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n", in tegra_adma_alloc_chan_resources()
677 ret = pm_runtime_resume_and_get(tdc2dev(tdc)); in tegra_adma_alloc_chan_resources()
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