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Searched refs:reg_offset (Results 1 – 25 of 319) sorted by relevance

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/Linux-v6.1/drivers/mfd/
Dsec-irq.c22 .reg_offset = 0,
26 .reg_offset = 0,
30 .reg_offset = 0,
34 .reg_offset = 0,
38 .reg_offset = 0,
42 .reg_offset = 0,
46 .reg_offset = 0,
50 .reg_offset = 0,
54 .reg_offset = 1,
58 .reg_offset = 1,
[all …]
Dda9052-irq.c37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 0,
57 .reg_offset = 0,
61 .reg_offset = 0,
65 .reg_offset = 0,
69 .reg_offset = 1,
73 .reg_offset = 1,
[all …]
Dwm5110-tables.c310 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
311 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
312 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
313 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
316 .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
319 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
322 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
325 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
[all …]
Dtps65910.c54 .reg_offset = 0,
58 .reg_offset = 0,
62 .reg_offset = 0,
66 .reg_offset = 0,
70 .reg_offset = 0,
74 .reg_offset = 0,
78 .reg_offset = 0,
82 .reg_offset = 0,
88 .reg_offset = 1,
92 .reg_offset = 1,
[all …]
Dpalmas.c73 .reg_offset = 1,
77 .reg_offset = 1,
81 .reg_offset = 1,
85 .reg_offset = 1,
89 .reg_offset = 1,
93 .reg_offset = 1,
97 .reg_offset = 1,
101 .reg_offset = 1,
106 .reg_offset = 2,
110 .reg_offset = 2,
[all …]
Dcs47l24-tables.c36 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
37 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
40 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
43 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
46 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
49 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
52 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
55 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
58 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
61 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
[all …]
Dmax8907.c116 { .reg_offset = 0, .mask = 1 << 0, },
117 { .reg_offset = 0, .mask = 1 << 1, },
118 { .reg_offset = 0, .mask = 1 << 2, },
119 { .reg_offset = 1, .mask = 1 << 0, },
120 { .reg_offset = 1, .mask = 1 << 1, },
121 { .reg_offset = 1, .mask = 1 << 2, },
122 { .reg_offset = 1, .mask = 1 << 3, },
123 { .reg_offset = 1, .mask = 1 << 4, },
124 { .reg_offset = 1, .mask = 1 << 5, },
125 { .reg_offset = 1, .mask = 1 << 6, },
[all …]
Dwm8994-irq.c28 .reg_offset = 1,
32 .reg_offset = 1,
36 .reg_offset = 1,
40 .reg_offset = 1,
44 .reg_offset = 1,
48 .reg_offset = 1,
52 .reg_offset = 1,
56 .reg_offset = 1,
60 .reg_offset = 1,
64 .reg_offset = 1,
[all …]
Das3722.c89 .reg_offset = 1,
93 .reg_offset = 1,
97 .reg_offset = 1,
101 .reg_offset = 1,
105 .reg_offset = 1,
109 .reg_offset = 1,
113 .reg_offset = 1,
117 .reg_offset = 1,
123 .reg_offset = 2,
127 .reg_offset = 2,
[all …]
Dmax14577.c193 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
194 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
195 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
197 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
198 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
199 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
200 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
201 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
203 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
204 { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
[all …]
Dwm8998-tables.c76 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
77 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
78 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
79 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
82 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
85 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
88 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
91 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
94 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
97 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
[all …]
Dwm5102-tables.c124 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
125 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
126 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
127 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
130 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
133 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
136 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
140 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
143 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
146 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
[all …]
Drk808.c326 .reg_offset = 0,
330 .reg_offset = 0,
334 .reg_offset = 0,
338 .reg_offset = 0,
342 .reg_offset = 0,
346 .reg_offset = 0,
350 .reg_offset = 0,
354 .reg_offset = 0,
362 .reg_offset = 0,
366 .reg_offset = 0,
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in arct_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in arct_reg_base_init()
43 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in arct_reg_base_init()
[all …]
Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in aldebaran_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
41 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in aldebaran_reg_base_init()
42 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in aldebaran_reg_base_init()
43 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in aldebaran_reg_base_init()
[all …]
Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
[all …]
Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
[all …]
Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
[all …]
Dsoc15_common.h28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
41 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
43 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
49 …__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, …
51 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
57 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
65 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
69 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_H…
72 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
82 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
[all …]
Djpeg_v1_0.c38 …_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) in jpeg_v1_0_decode_ring_patch_wreg() argument
42 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
43 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
45 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
47 ring->ring[(*ptr)++] = reg_offset; in jpeg_v1_0_decode_ring_patch_wreg()
57 uint32_t reg, reg_offset, val, mask, i; in jpeg_v1_0_decode_ring_set_patch_ring() local
61 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
63 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
67 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
69 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
[all …]
Dmmsch_v1_0.h61 uint32_t reg_offset : 28; member
66 uint32_t reg_offset : 20; member
99 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
102 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
109 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
112 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
121 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
124 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
Dsdma_v4_4.c40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; in sdma_v4_4_get_reg_offset()
163 uint32_t reg_offset, in sdma_v4_4_get_ras_error_count() argument
173 if (sdma_v4_4_ras_fields[i].reg_offset != reg_offset) in sdma_v4_4_get_ras_error_count()
198 uint32_t reg_offset = 0; in sdma_v4_4_query_ras_error_count_by_instance() local
200 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER); in sdma_v4_4_query_ras_error_count_by_instance()
201 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
207 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2); in sdma_v4_4_query_ras_error_count_by_instance()
208 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
235 uint32_t reg_offset; in sdma_v4_4_reset_ras_error_count() local
240 reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER); in sdma_v4_4_reset_ras_error_count()
[all …]
/Linux-v6.1/drivers/iommu/arm/arm-smmu/
Darm-smmu-qcom-debug.c20 const u32 *reg_offset; member
39 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS], in qcom_smmu_tlb_sync_debug()
45 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK], in qcom_smmu_tlb_sync_debug()
51 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR], in qcom_smmu_tlb_sync_debug()
71 .reg_offset = qcom_smmu_impl0_reg_offset,
75 .reg_offset = qcom_smmu_impl0_reg_offset,
79 .reg_offset = qcom_smmu_impl0_reg_offset,
83 .reg_offset = qcom_smmu_impl0_reg_offset,
87 .reg_offset = qcom_smmu_impl0_reg_offset,
91 .reg_offset = qcom_smmu_impl0_reg_offset,
[all …]
/Linux-v6.1/drivers/soc/qcom/
Dspm.c47 .reg_offset = spm_reg_offset_v4_1,
53 .reg_offset = spm_reg_offset_v4_1,
59 .reg_offset = spm_reg_offset_v4_1,
65 .reg_offset = spm_reg_offset_v4_1,
79 .reg_offset = spm_reg_offset_v3_0,
91 .reg_offset = spm_reg_offset_v3_0,
110 .reg_offset = spm_reg_offset_v2_1,
122 .reg_offset = spm_reg_offset_v2_1,
143 .reg_offset = spm_reg_offset_v1_1,
157 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
[all …]
/Linux-v6.1/drivers/input/misc/
Diqs7222.c472 int reg_offset; member
486 .reg_offset = 0,
494 .reg_offset = 0,
502 .reg_offset = 1,
510 .reg_offset = 1,
517 .reg_offset = 1,
524 .reg_offset = 1,
531 .reg_offset = 1,
540 .reg_offset = 2,
547 .reg_offset = 2,
[all …]

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