| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_ddi_buf_trans.c | 1226 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1255 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1280 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1305 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1332 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1351 if (crtc_state->port_clock > 540000) { in tgl_get_combo_buf_trans_edp()
1383 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1396 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1427 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1438 if (crtc_state->port_clock > 540000) { in rkl_get_combo_buf_trans_edp()
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| D | intel_dpll.c | 769 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
1149 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1160 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1223 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1233 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1248 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1259 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1297 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1304 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1335 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
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| D | g4x_dp.c | 77 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
96 pipe_config->port_clock, in intel_dp_prepare()
203 pipe_config->port_clock); in ilk_edp_pll_on()
207 if (pipe_config->port_clock == 162000) in ilk_edp_pll_on()
389 pipe_config->port_clock = 162000; in intel_dp_get_config()
391 pipe_config->port_clock = 270000; in intel_dp_get_config()
395 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
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| D | intel_ddi.c | 226 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
261 static u32 ddi_buf_phy_link_rate(int port_clock) in ddi_buf_phy_link_rate() argument
263 switch (port_clock) { in ddi_buf_phy_link_rate()
281 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
300 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
1023 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1219 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
1227 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1234 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
2282 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
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| D | intel_dp_link_training.c | 656 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, in intel_dp_prepare_link_train()
891 } else if (crtc_state->port_clock == 810000) { in intel_dp_training_pattern()
909 } else if (crtc_state->port_clock >= 540000) { in intel_dp_training_pattern()
1102 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1120 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
1418 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_128b132b_link_train()
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| D | intel_dpll_mgr.c | 958 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_compute_dpll()
965 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
988 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1008 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1064 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_compute_dpll()
1712 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, in skl_ddi_hdmi_pll_dividers()
1731 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1747 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2176 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2185 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
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| D | intel_dp.h | 74 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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| D | intel_dpio_phy.c | 917 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
919 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
921 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
923 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
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| D | intel_audio.c | 143 crtc_state->port_clock == dp_aud_n_m[i].clock) in audio_config_dp_get_n_m()
300 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
538 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
576 link_clk = crtc_state->port_clock; in calc_samples_room()
863 crtc_state->port_clock, in intel_audio_codec_enable()
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| D | intel_dp.c | 124 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
1134 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, in intel_dp_compute_rate() argument
1141 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1143 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1355 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1505 pipe_config->port_clock = limits->max_rate; in intel_dp_dsc_compute_config()
1521 pipe_config->port_clock, in intel_dp_dsc_compute_config()
1653 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1661 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1665 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
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| D | vlv_dsi_pll.c | 203 config->port_clock = pclk; in vlv_dsi_pll_compute()
529 config->port_clock = pclk; in bxt_dsi_pll_compute()
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| D | g4x_hdmi.c | 123 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); in intel_hdmi_get_config()
125 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
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| D | intel_tv.c | 1120 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1147 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1212 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
1220 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); in intel_tv_compute_config()
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| D | intel_crtc_state_dump.c | 257 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), in intel_crtc_state_dump()
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| D | intel_crt.c | 142 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
446 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
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| D | intel_display.c | 3145 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
3179 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
3335 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
4408 int port_clock; in i9xx_crtc_clock_get() local
4450 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
4452 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
4481 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
4489 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
4517 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in intel_crtc_dotclock()
4520 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
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| D | intel_dp_mst.c | 68 crtc_state->port_clock = limits->max_rate; in intel_dp_mst_compute_link_config()
100 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
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| D | intel_dvo.c | 184 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
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| D | intel_snps_phy.c | 1730 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) in intel_mpllb_calc_state()
1738 crtc_state->port_clock); in intel_mpllb_calc_state()
1748 if (crtc_state->port_clock == tables[i]->clock) { in intel_mpllb_calc_state()
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| D | intel_modeset_setup.c | 303 crtc_state->port_clock == 0; in has_bogus_dpll_config()
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| D | intel_lvds.c | 154 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
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| D | intel_cdclk.c | 2245 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2272 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2513 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
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| D | intel_display_types.h | 1149 int port_clock; member
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| D | intel_fdi.c | 227 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
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| D | intel_hdmi.c | 2130 crtc_state->port_clock = in intel_hdmi_compute_clock()
2299 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
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